-
Notifications
You must be signed in to change notification settings - Fork 68
Pull requests: intel/intel-xpu-backend-for-triton
Author
Label
Projects
Milestones
Reviews
Assignee
Sort
Pull requests list
Enable DAPS when sub-group-size=32 on GPU arch Xe+ and later.
#4869
opened Aug 11, 2025 by
chengjunlu
Loading…
[Coalescing]: Support layout propagation through
scf.if
nested in a loop
#4868
opened Aug 8, 2025 by
etiotto
Loading…
[Draft] Support the globaltimer and smid on Intel Arch
#4816
opened Jul 31, 2025 by
chengjunlu
•
Draft
[benchmarks] Reworked the conversion benchmark and added more tests for up/down casts
#4800
opened Jul 29, 2025 by
AndreyPavlenko
Loading…
A tracking utility for gathering the compile and/or runtime time, size, profiling and other statistics
#4777
opened Jul 25, 2025 by
AndreyPavlenko
Loading…
[LoadStoreToLLVM] Refactor the 2D block load lowering.
#4615
opened Jul 4, 2025 by
chengjunlu
Loading…
[EXPERIMENTAL]: Load column major matrix with 2d block io
#4604
opened Jul 2, 2025 by
chengjunlu
•
Draft
[Draft] [BACKEND] Enhance the remove layout implementation to reduce the duplicated values with different layout in scf.for.
#4527
opened Jun 18, 2025 by
chengjunlu
•
Draft
2
Clean up Intel specific code in the common TritonGPU dialect source file.
upstream: triton
#4469
opened Jun 10, 2025 by
chengjunlu
•
Draft
Do not use extractvalue if the inserted value is directly reachable
#4212
opened May 15, 2025 by
AndreyPavlenko
•
Draft
Use inline VISA to optimize horizontal batched subgroup reduce
#4171
opened May 12, 2025 by
chengjunlu
•
Draft
[SGLANG] [Benchmarks] Initial integration of sglang kernels to benchmarks
dependencies: igc
#3796
opened Mar 31, 2025 by
LiyangLingIntel
Loading…
Previous Next
ProTip!
Updated in the last three days: updated:>2025-08-07.