SystemVerilog Practice Repository

📘 About

The purpose of this repo is to:

• Practice all important topics in SystemVerilog.
• Understand and implement OOP principles.
• Work with mailboxes, constraints, inheritance, and randomization.
• Simulate mixed-language designs with Verilog (Design) + SystemVerilog (Testbench).
• Debug, test, and document various use cases that occur in real-world scenarios.

This repository is a comprehensive collection of my SystemVerilog and Verilog learning and practice code. It includes examples from:

• 📚 A Udemy SystemVerilog course
• 🛠️ The CHIPIN 4-day Verification using Assertions workshop by Synopsys
• ✍️ My own experiments and practice exercises

✅ All examples were tested and run using Vivado Simulator.
📂 Only the source files are included — no full project folders, to keep things clean and lightweight.

📘 Topics Covered

🧪 Testbench Basics

• Types of signals in a testbench
• Writing initial and always blocks
• Clock generation & edge alignment
• Using the timescale directive
• Parameter-controlled clocks

🔢 Data Types & Arrays

• Built-in and user-defined data types
• Static and dynamic arrays
• Array initialization methods
• Queue operations and use cases

🔁 Control Structures

• Looping structures (for, foreach, etc.)
• Conditional logic (if, else, ternary)

🧱 Object-Oriented Programming

• Defining classes and using constructors
• Inheritance and polymorphism
• Passing by value vs reference
• Shallow vs deep object copying
• Functions and tasks in classes

🎲 Randomization & Constraints

• Writing and controlling constraints
• randc and weighted distributions
• Turning constraints ON/OFF
• Pre and post-randomization methods

🔄 Interprocess Communication

• Events, @, and wait
• Using fork-join, fork-join_any, fork-join_none
• Semaphores and mailboxes (including parameterized mailboxes)

🔌 Using Interfaces

• Declaring and connecting interfaces to DUTs
• Blocking vs non-blocking assignments in interfaces
• Using modports to separate roles
• Driving signals with interfaces

🧰 Testbench Components

• Creating generators, drivers, monitors, and scoreboards
• Injecting errors to test robustness
• Implementing simple scoreboard models