UVM YAPP Router Verification Environment

A comprehensive UVM (Universal Verification Methodology) testbench for verifying a YAPP (Yet Another Packet Protocol) Router design. This project demonstrates advanced UVM sequence generation, virtual interface implementation, and SystemVerilog testbench development using the Cadence Xcelium simulator.

Project Overview

This verification environment implements a complete UVM testbench for a packet router handling YAPP protocol packets. It emphasizes virtual interface-based verification, advanced sequence generation, and constraint-based randomization for rigorous design verification.

Key Features

UVM-based Verification Environment with a full testbench hierarchy
Virtual Interface Implementation separating testbench and DUT cleanly
Advanced Sequence Generation with diverse sequence types and patterns
Constraint-based Randomization to achieve wide test coverage
Transaction Recording to aid in debugging and analysis
Coverage Analysis including functional and code coverage
Multiple Test Scenarios for varied verification goals
Cadence Xcelium Integration for efficient simulation workflows

Project Structure

NCDC_DV_Lab_39/
├── lab39_vif/
│   ├── sv/
│   │   ├── yapp_packet.sv
│   │   ├── yapp_tx_driver.sv
│   │   ├── yapp_tx_monitor.sv  
│   │   ├── yapp_tx_sequencer.sv
│   │   ├── yapp_tx_agent.sv
│   │   ├── yapp_tx_seqs.sv
│   │   ├── yapp_env.sv
│   │   ├── yapp_if.sv
│   │   ├── yapp_pkg.sv
│   │   ├── driver_example.sv
│   │   └── monitor_example.sv
│   └── tb/
│       ├── router_test_lib.sv
│       ├── tb_top.sv
│       ├── xcelium.d/
│       ├── .simvision/
│       └── .uvmtclcomm.txt
├── router_rtl/
│   └── yapp_router.sv
├── .gitignore
└── README.md

Getting Started

Prerequisites

Cadence Xcelium (v23.09 or newer)
UVM 1.1d or newer
SystemVerilog (IEEE 1800-2017) support
Linux OS (tested on RHEL/CentOS)
Valid Cadence license

Setup

git clone <repository-url>
cd NCDC_DV_Lab_39

export XCELIUM_HOME=/path/to/xcelium
export PATH=$XCELIUM_HOME/tools/bin:$PATH

xlicmgr -p  # Check license

Running Simulations

Navigate to:

cd lab39_vif/tb

Example Commands

xrun -f file.f -access +rwc -uvm +UVM_TESTNAME=base_test
xrun -f file.f -access +rwc -uvm +UVM_TESTNAME=base_test +SVSEED=random
xrun -f file.f -access +rwc -uvm +UVM_TESTNAME=base_test +SVSEED=random -gui
xrun -f file.f -access +rwc -uvm +UVM_VERBOSITY=UVM_HIGH

Test Scenarios

Available Test Classes

Test Class	Description	Sequence	Purpose
base_test	Basic packet test	yapp_5_packets	5 random packets
short_packet_test	Payload size 1-14, no addr 2	yapp_5_packets	Edge case test
set_config_test	Passive agent configuration	yapp_5_packets	Agent mode test
incr_payload_test	Increasing payload sizes	yapp_incr_payload_seq	Pattern testing
yapp_012_test	Address 0,1,2 test	yapp_012_seq	Address coverage
yapp_111_test	Repeated addr 1	yapp_111_seq	Stress test on one address
exhaustive_seq_test	All sequences	yapp_exhaustive_seq	Full coverage run

Sequence Library

Sequence Class	Purpose	Count	Notes
yapp_base_seq	Base class	Variable	Parent class for sequences
yapp_5_packets	Basic sequence	5	Randomized full constraint
yapp_1_seq	Simple test	1	Address 1 only
yapp_012_seq	Address 0,1,2	3	Coverage test
yapp_111_seq	Same address test	3	Repeated packets
yapp_repeat_addr_seq	Fixed random address	5	Stress one address
yapp_incr_payload_seq	Pattern test	6	Sizes from 1 to 6
yapp_rnd_seq	Random count	1–10	Dynamic length
yapp_exhaustive_seq	All types combined	Variable	Test all types

Sample Test Commands

xrun -f file.f -access +rwc -uvm +UVM_TESTNAME=short_packet_test
xrun -f file.f -access +rwc -uvm +UVM_TESTNAME=incr_payload_test
xrun -f file.f -access +rwc -uvm +UVM_TESTNAME=yapp_012_test
xrun -f file.f -access +rwc -uvm +UVM_TESTNAME=exhaustive_seq_test

Key Components

Packet Format

Header: 8 bits = [Length: 6 bits | Address: 2 bits]
Payload: 1–63 bytes
Parity: 8-bit XOR of header + payload

Virtual Interface

Clock/reset handling
Signal mapping for DUT
Pause/resume control
Payload memory support
UVM transaction triggering

Component Hierarchy

yapp_env
├── yapp_tx_agent (configurable: active/passive)
│   ├── yapp_tx_sequencer
│   ├── yapp_tx_driver
│   └── yapp_tx_monitor
└── Configuration objects

Constraints

yapp_packet: Full range (addr 0–2, payload 1–63)
short_yapp_packet: Payload ≤ 14, no addr 2

Verification Metrics

Coverage Goals

Functional: Address use, payload sizes, boundary tests, errors
Code: >95% line, >90% branch, 100% FSM, >85% toggle
Assertions: Protocol, timing, data checks

Debug Tools

+UVM_TR_RECORD +UVM_LOG_RECORD         # Transaction recording
xrun -f file.f -coverage all -covoverwrite  # Coverage
simvision waves.shm &                  # Waveforms

Development Guide

New Sequence

class my_seq extends yapp_base_seq;
  `uvm_object_utils(my_seq)

  virtual task body();
    // Your logic here
  endtask
endclass

New Test

class my_test extends base_test;
  `uvm_component_utils(my_test)

  virtual function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    // Setup
  endfunction
endclass

Configuration

uvm_config_db#(virtual yapp_if)::set(this, "*", "vif", yapp_vif);

Optimization Tips

Use payload memory
Limit logging unless needed
Use -memmonitor for memory tracking
Compile using -compile -elaborate for speed

Debugging

Common Issues

Missing interface

if (!uvm_config_db#(virtual yapp_if)::get(this, "", "vif", vif))
  `uvm_fatal("NOVIF", "Virtual interface not found")

Randomization failure

if (!packet.randomize())
  `uvm_error("RAND_FAIL", "Randomization failed")

Objections

phase.raise_objection(this);
// ...
phase.drop_objection(this);

Logging

+UVM_VERBOSITY=UVM_HIGH
+uvm_set_verbosity=*driver*,UVM_HIGH

Documentation

UVM 1.1d Guide
IEEE 1800-2017 LRM
Cadence Xcelium Docs
Lab documentation

Code Examples

Sequence

class simple_seq extends yapp_base_seq;
  `uvm_object_utils(simple_seq)

  virtual task body();
    yapp_packet pkt;
    repeat(3) begin
      pkt = yapp_packet::type_id::create("pkt");
      start_item(pkt);
      assert(pkt.randomize());
      finish_item(pkt);
    end
  endtask
endclass

Custom Constraint

class large_packet extends yapp_packet;
  constraint large_payload { length inside {[50:63]}; }
  `uvm_object_utils(large_packet)
endclass

Contributing

Workflow

Fork → Branch → Develop → Test → Pull Request
Follow SystemVerilog coding standards

Standards

Snake_case for signals, PascalCase for classes
2-space indentation
Doxygen-style comments

Tests

Unit, Integration, Regression, and Performance

License

This project is provided under the Cadence Academic License for educational use only.

Support

UVM help: UVM Guide
Cadence issues: Contact Cadence
Lab support: Lab docs
Bugs: Open GitHub issue

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
lab39_vif		lab39_vif
router_rtl		router_rtl
.gitignore		.gitignore
README.md		README.md

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