From 95fc56004cbccf73b488c25528f1346d1fa6e0a4 Mon Sep 17 00:00:00 2001 From: Scott Worley Date: Fri, 1 Aug 2025 17:30:22 -0400 Subject: [PATCH 1/3] dts: arm: microchip: mec: Add MEC165xB chip device tree files We add MEC165xB chip device tree files. We are sharing the same base mec5.dtsi which required modifications due to peripherals not present in MEC165xB. Signed-off-by: Scott Worley --- dts/arm/microchip/mec/mec5.dtsi | 26 +--------- dts/arm/microchip/mec/mec5/mec5_bclink.dtsi | 17 +++++++ .../microchip/mec/mec5/mec5_pkg176_uarts.dtsi | 25 ---------- dts/arm/microchip/mec/mec5/mec5_rcid.dtsi | 30 ++++++++++++ dts/arm/microchip/mec/mec5_mec1653bnsz.dtsi | 48 +++++++++++++++++++ dts/arm/microchip/mec/mec5_mec1743qlj.dtsi | 33 ++++++++++++- dts/arm/microchip/mec/mec5_mec1743qsz.dtsi | 20 +++++++- dts/arm/microchip/mec/mec5_mec1753qlj.dtsi | 32 ++++++++++++- dts/arm/microchip/mec/mec5_mec1753qsz.dtsi | 20 +++++++- dts/arm/microchip/mec/mec5_mech1723nlj.dtsi | 8 ++++ dts/arm/microchip/mec/mec5_mech1723nsz.dtsi | 8 ++++ 11 files changed, 211 insertions(+), 56 deletions(-) create mode 100644 dts/arm/microchip/mec/mec5/mec5_bclink.dtsi delete mode 100644 dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi create mode 100644 dts/arm/microchip/mec/mec5/mec5_rcid.dtsi create mode 100644 dts/arm/microchip/mec/mec5_mec1653bnsz.dtsi diff --git a/dts/arm/microchip/mec/mec5.dtsi b/dts/arm/microchip/mec/mec5.dtsi index 8ee4948a95065..90879ab6dabec 100644 --- a/dts/arm/microchip/mec/mec5.dtsi +++ b/dts/arm/microchip/mec/mec5.dtsi @@ -267,6 +267,7 @@ compatible = "microchip,xec-basic-timer"; reg = <0x40000ca0 0x20>; interrupts = <141 0>; + girqs = <23 5>; clock-frequency = <48000000>; prescaler = <0>; max-value = <0xffffffff>; @@ -488,21 +489,6 @@ interrupts = <87 0>; status = "disabled"; }; - rcid0: rcid@40001400 { - reg = <0x40001400 0x80>; - interrupts = <80 0>; - status = "disabled"; - }; - rcid1: rcid@40001480 { - reg = <0x40001480 0x80>; - interrupts = <81 0>; - status = "disabled"; - }; - rcid2: rcid@40001500 { - reg = <0x40001500 0x80>; - interrupts = <82 0>; - status = "disabled"; - }; bbled0: bbled@4000b800 { reg = <0x4000b800 0x100>; interrupts = <83 0>; @@ -518,16 +504,6 @@ interrupts = <85 0>; status = "disabled"; }; - bbled3: bbled@4000bb00 { - reg = <0x4000bb00 0x100>; - interrupts = <86 0>; - status = "disabled"; - }; - bclink0: bclink@4000cd00 { - reg = <0x4000cd00 0x20>; - interrupts = <96 0>, <97 0>; - status = "disabled"; - }; tfdp0: tfdp@40008c00 { reg = <0x40008c00 0x10>; status = "disabled"; diff --git a/dts/arm/microchip/mec/mec5/mec5_bclink.dtsi b/dts/arm/microchip/mec/mec5/mec5_bclink.dtsi new file mode 100644 index 0000000000000..489a26db3f92f --- /dev/null +++ b/dts/arm/microchip/mec/mec5/mec5_bclink.dtsi @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* From Microchip MEC5 MEC174x and onwards includes one instance of the + * BC-Link peripheral. + * Include this file in the soc {} section in the relevant chip DTSI files + */ +bclink0: bclink@4000cd00 { + reg = <0x4000cd00 0x20>; + interrupts = <96 3>, <97 3>; + interrupt-names = "bcm_err", "bcm_done"; + girqs = <18 7>, <18 6>; + status = "disabled"; +}; diff --git a/dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi b/dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi deleted file mode 100644 index b1ebea4552707..0000000000000 --- a/dts/arm/microchip/mec/mec5/mec5_pkg176_uarts.dtsi +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2024 Microchip Technology Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Microchip MEC5 MEC174x, MEC540x, MEC175x, and MEC550x add two more UART's - * in the 176-pin (LJ) package. - * Include this file in the soc {} section in the above chip DTSI files. - */ -uart2: uart@400f2c00 { - reg = <0x400f2c00 0x400>; - interrupts = <183 1>; - clock-frequency = <1843200>; - current-speed = <38400>; - status = "disabled"; -}; - -uart3: uart@400f3000 { - reg = <0x400f3000 0x400>; - interrupts = <184 1>; - clock-frequency = <1843200>; - current-speed = <38400>; - status = "disabled"; -}; diff --git a/dts/arm/microchip/mec/mec5/mec5_rcid.dtsi b/dts/arm/microchip/mec/mec5/mec5_rcid.dtsi new file mode 100644 index 0000000000000..3f24d866c88f4 --- /dev/null +++ b/dts/arm/microchip/mec/mec5/mec5_rcid.dtsi @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* From Microchip MEC5 MEC174x and onwards include three instances of the + * RC-ID peripheral. + * Include this file in the soc {} section in the relevant chip DTSI files + */ +rcid0: rcid@40001400 { + reg = <0x40001400 0x80>; + interrupts = <80 3>; + girqs = <17 10>; + status = "disabled"; +}; + +rcid1: rcid@40001480 { + reg = <0x40001480 0x80>; + interrupts = <81 3>; + girqs = <17 11>; + status = "disabled"; +}; + +rcid2: rcid@40001500 { + reg = <0x40001500 0x80>; + interrupts = <82 3>; + girqs = <17 12>; + status = "disabled"; +}; diff --git a/dts/arm/microchip/mec/mec5_mec1653bnsz.dtsi b/dts/arm/microchip/mec/mec5_mec1653bnsz.dtsi new file mode 100644 index 0000000000000..39c0fad387de2 --- /dev/null +++ b/dts/arm/microchip/mec/mec5_mec1653bnsz.dtsi @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#include "mec5.dtsi" + +/ { + flash0: flash@b0000 { + reg = <0x000b0000 0x58000>; + }; + + sram0: memory@118000 { + compatible = "mmio-sram"; + reg = <0x00118000 0xf800>; + }; + + soc { + #include "mec5/mec5_dma_chan20.dtsi" + #include "mec5/mec5_eeprom_8kb.dtsi" + #include "mec5/mec5_i3c.dtsi" + + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + kscan0: kscan@40009c00 { + reg = <0x40009c00 0x18>; + interrupts = <135 0>; + status = "disabled"; + }; + + uart2: uart@400f2c00 { + reg = <0x400f2c00 0x400>; + interrupts = <183 2>; + clock-frequency = <1843200>; + current-speed = <115200>; + status = "disabled"; + }; + }; +}; diff --git a/dts/arm/microchip/mec/mec5_mec1743qlj.dtsi b/dts/arm/microchip/mec/mec5_mec1743qlj.dtsi index 694e95fa885ef..15e921ec9d1a4 100644 --- a/dts/arm/microchip/mec/mec5_mec1743qlj.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1743qlj.dtsi @@ -23,12 +23,43 @@ #include "mec5/mec5_gpspi_v2.dtsi" #include "mec5/mec5_eeprom_8kb.dtsi" #include "mec5/mec5_pkg176_pwms.dtsi" - #include "mec5/mec5_pkg176_uarts.dtsi" + #include "mec5/mec5_rcid.dtsi" + #include "mec5/mec5_bclink.dtsi" + + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; status = "disabled"; }; + + bbled3: bbled@4000bb00 { + reg = <0x4000bb00 0x100>; + interrupts = <86 3>; + status = "disabled"; + }; + + uart2: uart@400f2c00 { + reg = <0x400f2c00 0x400>; + interrupts = <183 2>; + clock-frequency = <1843200>; + current-speed = <115200>; + status = "disabled"; + }; + + uart3: uart@400f3000 { + reg = <0x400f3000 0x400>; + interrupts = <184 2>; + clock-frequency = <1843200>; + current-speed = <115200>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/microchip/mec/mec5_mec1743qsz.dtsi b/dts/arm/microchip/mec/mec5_mec1743qsz.dtsi index 5d16b727bf5c3..a76d3ac0a1b87 100644 --- a/dts/arm/microchip/mec/mec5_mec1743qsz.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1743qsz.dtsi @@ -22,6 +22,16 @@ #include "mec5/mec5_dma_chan16.dtsi" #include "mec5/mec5_gpspi_v2.dtsi" #include "mec5/mec5_eeprom_8kb.dtsi" + #include "mec5/mec5_rcid.dtsi" + #include "mec5/mec5_bclink.dtsi" + + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; @@ -29,11 +39,17 @@ status = "disabled"; }; + bbled3: bbled@4000bb00 { + reg = <0x4000bb00 0x100>; + interrupts = <86 3>; + status = "disabled"; + }; + uart2: uart@400f2c00 { reg = <0x400f2c00 0x400>; - interrupts = <183 1>; + interrupts = <183 2>; clock-frequency = <1843200>; - current-speed = <38400>; + current-speed = <115200>; status = "disabled"; }; }; diff --git a/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi b/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi index d7bacf673535f..3bf91e116d9e9 100644 --- a/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi @@ -23,8 +23,17 @@ #include "mec5/mec5_eeprom_8kb.dtsi" #include "mec5/mec5_gpspi_v2.dtsi" #include "mec5/mec5_pkg176_pwms.dtsi" - #include "mec5/mec5_pkg176_uarts.dtsi" #include "mec5/mec5_i3c.dtsi" + #include "mec5/mec5_rcid.dtsi" + #include "mec5/mec5_bclink.dtsi" + + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; @@ -32,5 +41,26 @@ status = "disabled"; }; + bbled3: bbled@4000bb00 { + reg = <0x4000bb00 0x100>; + interrupts = <86 3>; + status = "disabled"; + }; + + uart2: uart@400f2c00 { + reg = <0x400f2c00 0x400>; + interrupts = <183 2>; + clock-frequency = <1843200>; + current-speed = <115200>; + status = "disabled"; + }; + + uart3: uart@400f3000 { + reg = <0x400f3000 0x400>; + interrupts = <184 2>; + clock-frequency = <1843200>; + current-speed = <115200>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/microchip/mec/mec5_mec1753qsz.dtsi b/dts/arm/microchip/mec/mec5_mec1753qsz.dtsi index df30851445728..893af2bbb4785 100644 --- a/dts/arm/microchip/mec/mec5_mec1753qsz.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1753qsz.dtsi @@ -23,6 +23,16 @@ #include "mec5/mec5_eeprom_8kb.dtsi" #include "mec5/mec5_gpspi_v2.dtsi" #include "mec5/mec5_i3c.dtsi" + #include "mec5/mec5_rcid.dtsi" + #include "mec5/mec5_bclink.dtsi" + + ps2_1: ps2@40009040 { + reg = <0x40009040 0x40>; + interrupts = <101 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; @@ -30,11 +40,17 @@ status = "disabled"; }; + bbled3: bbled@4000bb00 { + reg = <0x4000bb00 0x100>; + interrupts = <86 3>; + status = "disabled"; + }; + uart2: uart@400f2c00 { reg = <0x400f2c00 0x400>; - interrupts = <183 1>; + interrupts = <183 2>; clock-frequency = <1843200>; - current-speed = <38400>; + current-speed = <115200>; status = "disabled"; }; }; diff --git a/dts/arm/microchip/mec/mec5_mech1723nlj.dtsi b/dts/arm/microchip/mec/mec5_mech1723nlj.dtsi index 82a0aa2b2e048..fdc0fb0418202 100644 --- a/dts/arm/microchip/mec/mec5_mech1723nlj.dtsi +++ b/dts/arm/microchip/mec/mec5_mech1723nlj.dtsi @@ -23,11 +23,19 @@ #include "mec5/mec5_gpspi_v1.dtsi" #include "mec5/mec5_eeprom_8kb.dtsi" #include "mec5/mec5_pkg176_pwms.dtsi" + #include "mec5/mec5_rcid.dtsi" + #include "mec5/mec5_bclink.dtsi" kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; status = "disabled"; }; + + bbled3: bbled@4000bb00 { + reg = <0x4000bb00 0x100>; + interrupts = <86 3>; + status = "disabled"; + }; }; }; diff --git a/dts/arm/microchip/mec/mec5_mech1723nsz.dtsi b/dts/arm/microchip/mec/mec5_mech1723nsz.dtsi index 02cdbab26fc69..db17c4c435fea 100644 --- a/dts/arm/microchip/mec/mec5_mech1723nsz.dtsi +++ b/dts/arm/microchip/mec/mec5_mech1723nsz.dtsi @@ -22,11 +22,19 @@ #include "mec5/mec5_dma_chan16.dtsi" #include "mec5/mec5_gpspi_v1.dtsi" #include "mec5/mec5_eeprom_8kb.dtsi" + #include "mec5/mec5_rcid.dtsi" + #include "mec5/mec5_bclink.dtsi" kscan0: kscan@40009c00 { reg = <0x40009c00 0x18>; interrupts = <135 0>; status = "disabled"; }; + + bbled3: bbled@4000bb00 { + reg = <0x4000bb00 0x100>; + interrupts = <86 3>; + status = "disabled"; + }; }; }; From 1482de34e32353b729d40ab90a837c2a1db40db9 Mon Sep 17 00:00:00 2001 From: Scott Worley Date: Fri, 1 Aug 2025 17:07:02 -0400 Subject: [PATCH 2/3] soc: microchip: mec: Add MEC165xB chip series We add Microchip MEC165xB SoC series. Signed-off-by: Scott Worley --- soc/microchip/mec/mec165xb/CMakeLists.txt | 11 +++++++ soc/microchip/mec/mec165xb/Kconfig | 13 ++++++++ .../mec/mec165xb/Kconfig.defconfig.series | 31 +++++++++++++++++++ soc/microchip/mec/mec165xb/Kconfig.soc | 20 ++++++++++++ soc/microchip/mec/mec165xb/soc.c | 16 ++++++++++ soc/microchip/mec/mec165xb/soc.h | 24 ++++++++++++++ soc/microchip/mec/soc.yml | 3 ++ 7 files changed, 118 insertions(+) create mode 100644 soc/microchip/mec/mec165xb/CMakeLists.txt create mode 100644 soc/microchip/mec/mec165xb/Kconfig create mode 100644 soc/microchip/mec/mec165xb/Kconfig.defconfig.series create mode 100644 soc/microchip/mec/mec165xb/Kconfig.soc create mode 100644 soc/microchip/mec/mec165xb/soc.c create mode 100644 soc/microchip/mec/mec165xb/soc.h diff --git a/soc/microchip/mec/mec165xb/CMakeLists.txt b/soc/microchip/mec/mec165xb/CMakeLists.txt new file mode 100644 index 0000000000000..f8f479c1264df --- /dev/null +++ b/soc/microchip/mec/mec165xb/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2025, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources(soc.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/mec/mec165xb/Kconfig b/soc/microchip/mec/mec165xb/Kconfig new file mode 100644 index 0000000000000..79ff7dd7e0fb8 --- /dev/null +++ b/soc/microchip/mec/mec165xb/Kconfig @@ -0,0 +1,13 @@ +# Microchip MEC165XB MCU core series + +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC165XB + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_MEC5_HAL + select SOC_PREP_HOOK diff --git a/soc/microchip/mec/mec165xb/Kconfig.defconfig.series b/soc/microchip/mec/mec165xb/Kconfig.defconfig.series new file mode 100644 index 0000000000000..1c554a7fa4d36 --- /dev/null +++ b/soc/microchip/mec/mec165xb/Kconfig.defconfig.series @@ -0,0 +1,31 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Microchip MEC165xB MCU series configuration options + +if SOC_SERIES_MEC165XB + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # All NVIC external sources. + default 198 + +config CORTEX_M_SYSTICK + depends on !MCHP_XEC_RTOS_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK + default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency) if MCHP_XEC_RTOS_TIMER + +if MCHP_XEC_RTOS_TIMER + +config SYS_CLOCK_TICKS_PER_SEC + default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency) + +endif # MCHP_XEC_RTOS_TIMER + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y + +endif # SOC_SERIES_MEC165XB diff --git a/soc/microchip/mec/mec165xb/Kconfig.soc b/soc/microchip/mec/mec165xb/Kconfig.soc new file mode 100644 index 0000000000000..49544c0b66dc5 --- /dev/null +++ b/soc/microchip/mec/mec165xb/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +# Microchip MEC165xB MCU core series + +config SOC_SERIES_MEC165XB + bool + select SOC_FAMILY_MICROCHIP_MEC + help + Enable support for Microchip MEC Cortex-M4 MCU series + +config SOC_SERIES + default "mec165xb" if SOC_SERIES_MEC165XB + +config SOC_MEC1653B_NSZ + bool + select SOC_SERIES_MEC165XB + +config SOC + default "mec1653b_nsz" if SOC_MEC1653B_NSZ diff --git a/soc/microchip/mec/mec165xb/soc.c b/soc/microchip/mec/mec165xb/soc.c new file mode 100644 index 0000000000000..20028ed20b0fe --- /dev/null +++ b/soc/microchip/mec/mec165xb/soc.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +void soc_prep_hook(void) +{ + mec5_soc_common_init(); +} diff --git a/soc/microchip/mec/mec165xb/soc.h b/soc/microchip/mec/mec165xb/soc.h new file mode 100644 index 0000000000000..e1b1ab8ec1426 --- /dev/null +++ b/soc/microchip/mec/mec165xb/soc.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2025 Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __SOC_MICROCHIP_MEC_MEC165XB_SOC_H +#define __SOC_MICROCHIP_MEC_MEC165XB_SOC_H + +#define SYSCLK_DEFAULT_IOSC_HZ MHZ(96) + +#ifndef _ASMLANGUAGE + +#include "device_mec5.h" + +/* common SoC API */ +#include "soc_dt.h" +#include "soc_espi_channels.h" +#include "soc_gpio.h" +#include "soc_pcr.h" +#include "soc_pins.h" + +#endif +#endif diff --git a/soc/microchip/mec/soc.yml b/soc/microchip/mec/soc.yml index b3c68a80ed069..b5e215314c412 100644 --- a/soc/microchip/mec/soc.yml +++ b/soc/microchip/mec/soc.yml @@ -4,6 +4,9 @@ family: - name: mec15xx socs: - name: mec1501_hsz + - name: mec165xb + socs: + - name: mec1653b_nsz - name: mec172x socs: - name: mec172x_nsz From 5ad1a937192b49ae386c0068ac1e1d3aa93f7d5c Mon Sep 17 00:00:00 2001 From: Scott Worley Date: Fri, 1 Aug 2025 17:42:23 -0400 Subject: [PATCH 3/3] boards: microchip: mec_assy6941: Add support for MEC1653B We added support for the MEC1653B daughter card on the mec_assy6941 EVB base board. Signed-off-by: Scott Worley --- .../mec_assy6941/Kconfig.mec_assy6941 | 1 + .../Kconfig.mec_assy6941_mec1653b_nsz | 5 ++ boards/microchip/mec_assy6941/board.yml | 1 + .../mec_assy6941_mec1653b_nsz.dts | 66 +++++++++++++++++++ .../mec_assy6941_mec1653b_nsz.yaml | 25 +++++++ .../mec_assy6941_mec1653b_nsz_defconfig | 8 +++ 6 files changed, 106 insertions(+) create mode 100644 boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1653b_nsz create mode 100644 boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.dts create mode 100644 boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.yaml create mode 100644 boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz_defconfig diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941 b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941 index 85a094ac8d1d7..439601698dbbe 100644 --- a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941 +++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941 @@ -2,6 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_MEC_ASSY6941 + select SOC_MEC1653B_NSZ if BOARD_MEC_ASSY6941_MEC1653B_NSZ select SOC_MEC1743_QLJ if BOARD_MEC_ASSY6941_MEC1743_QLJ select SOC_MEC1743_QSZ if BOARD_MEC_ASSY6941_MEC1743_QSZ select SOC_MEC1753_QLJ if BOARD_MEC_ASSY6941_MEC1753_QLJ diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1653b_nsz b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1653b_nsz new file mode 100644 index 0000000000000..90c93b0577d6c --- /dev/null +++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1653b_nsz @@ -0,0 +1,5 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC_ASSY6941_MEC1653B_NSZ + select SOC_MEC1653B_NSZ diff --git a/boards/microchip/mec_assy6941/board.yml b/boards/microchip/mec_assy6941/board.yml index 2849b6b8a08f1..daa9bee52d0b9 100644 --- a/boards/microchip/mec_assy6941/board.yml +++ b/boards/microchip/mec_assy6941/board.yml @@ -3,6 +3,7 @@ board: full_name: MEC17xxEVB ASSY6941 vendor: microchip socs: + - name: mec1653b_nsz - name: mec1743_qlj - name: mec1743_qsz - name: mec1753_qlj diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.dts new file mode 100644 index 0000000000000..44129cbf3b0c9 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.dts @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2025, Microchip Technology Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "Microchip MEC ASSY6941 MEC1753B-NSZ evaluation board"; + compatible = "microchip,mec_assy6941-mec1653b_nsz"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,console = &uart1; + rtimer-busy-wait-timer = &timer5; + }; + + power-states { + idle: idle { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + min-residency-us = <1000000>; + }; + + suspend_to_ram: suspend_to_ram { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-ram"; + min-residency-us = <2000000>; + }; + }; +}; + +&cpu0 { + clock-frequency = <96000000>; + status = "okay"; + cpu-power-states = <&idle &suspend_to_ram>; +}; + +/* Disable ARM SysTick kernel timer driver */ +&systick { + status = "disabled"; +}; + +/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */ +&rtimer { + status = "okay"; +}; + +/* We chose 32-bit basic timer 5 for use by ktimer */ +&timer5 { + status = "okay"; +}; + +&uart1 { + compatible = "microchip,mec5-uart"; + status = "okay"; + clock-frequency = <1843200>; + current-speed = <115200>; + pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>; + pinctrl-names = "default"; +}; diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.yaml new file mode 100644 index 0000000000000..5c6846e5a8b10 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz.yaml @@ -0,0 +1,25 @@ +# +# Copyright (c) 2025, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mec_assy6941/mec1653b_nsz +name: MEC174X EVB ASSY 6941 with MEC1653B-NSZ +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +ram: 60 +flash: 352 +supported: + - gpio + - pinctrl +testing: + binaries: + - spi_image.bin + ignore_tags: + - bluetooth + - net +vendor: microchip diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz_defconfig new file mode 100644 index 0000000000000..47eaa31ebd3f6 --- /dev/null +++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1653b_nsz_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2025, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y