soc: nxp: kinetis: ke1xz: add LPFLL clock support to SCG

LPFLL (soc: scg: "lpfll_clk") clock source can be now selected
in KE1xz Device tree (nxp_ke1xz.dtsi., board.dts or overlay)
Tested on boards: frdm_ke15z, frdm_ke17z, frdm_ke17z512

Signed-off-by: Michael Galda <michael.galda@nxp.com>

Author: mgalda82

boards/nxp/frdm_ke17z512/frdm_ke17z512.dts

@@ -116,7 +116,7 @@
 
 &scg {
 	bus_clk {
-		clock-div = <2>;
+		clock-div = <4>;
 	};
 };
 

drivers/clock_control/clock_control_mcux_scg.c

@@ -69,7 +69,7 @@ static int mcux_scg_get_rate(const struct device *dev,
 		break;
 #endif /* (defined(FSL_FEATURE_SCG_HAS_SPLL) && FSL_FEATURE_SCG_HAS_SPLL) */
 #if (defined(FSL_FEATURE_SCG_HAS_LPFLL) && FSL_FEATURE_SCG_HAS_LPFLL)
-	case KINETIS_SCG_SPLL_CLK:
+	case KINETIS_SCG_LPFLL_CLK:
 		clock_name = kCLOCK_ScgLpFllClk;
 		break;
 #endif /* (defined(FSL_FEATURE_SCG_HAS_LPFLL) && FSL_FEATURE_SCG_HAS_LPFLL) */
@@ -136,6 +136,8 @@ static int mcux_scg_init(const struct device *dev)
 	CLOCK_SetClkOutSel(kClockClkoutSelFirc);
 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(spll_clk))
 	CLOCK_SetClkOutSel(kClockClkoutSelSysPll);
+#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(lpfll_clk))
+	CLOCK_SetClkOutSel(kClockClkoutSelSysLpfll);
 #else
 #error Unsupported SCG clkout clock source
 #endif

dts/arm/nxp/nxp_ke1xz.dtsi

@@ -89,9 +89,16 @@
 				#clock-cells = <0>;
 			};
 
+			lpfll_clk: lpfll_clk {
+				compatible = "fixed-clock";
+				clock-frequency = <72000000>;
+				#clock-cells = <0>;
+			};
+
 			core_clk: core_clk {
 				compatible = "fixed-factor-clock";
-				clocks = <&firc_clk>;
+				#clocks = <&firc_clk>;
+				clocks = <&lpfll_clk>;
 				clock-div = <1>;
 				#clock-cells = <0>;
 			};
@@ -116,6 +123,13 @@
 				clock-div = <1>;
 				#clock-cells = <0>;
 			};
+
+			flldiv2_clk: flldiv2_clk {
+				compatible = "fixed-factor-clock";
+				clocks = <&lpfll_clk>;
+				clock-div = <2>;
+				#clock-cells = <0>;
+			};
 		};
 
 		pcc: pcc@40065000 {

include/zephyr/dt-bindings/clock/kinetis_scg.h

@@ -29,5 +29,6 @@
 #define KINETIS_SCG_FIRC_ASYNC_DIV2_CLK 13U
 #define KINETIS_SCG_SPLL_ASYNC_DIV1_CLK 14U
 #define KINETIS_SCG_SPLL_ASYNC_DIV2_CLK 15U
+#define KINETIS_SCG_LPFLL_CLK           16U
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_ */

soc/nxp/kinetis/ke1xz/soc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024, 2025 NXP
  * Copyright (c) 2019-2021 Vestas Wind Systems A/S
  *
  * Based on NXP k6x soc.c, which is:
@@ -43,13 +43,19 @@ static const scg_sys_clk_config_t scg_sys_clk_config = {
 	.src     = kSCG_SysClkSrcSirc,
 #elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(firc_clk))
 	.src     = kSCG_SysClkSrcFirc,
+#elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(lpfll_clk))
+	.src     = kSCG_SysClkSrcLpFll,
+#elif DT_SAME_NODE(DT_CLOCKS_CTLR(SCG_CLOCK_NODE(core_clk)), SCG_CLOCK_NODE(sosc_clk))
+	.src     = kSCG_SysClkSrcSysOsc,
+#else
+#error Invalid SCG core clock selected
 #endif
 };
 
 /* Slow Internal Reference Clock (SIRC) configuration */
 ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(sircdiv2_clk),
 		       "Invalid SCG SIRC divider 2 value");
-static const scg_sirc_config_t scg_sirc_config = {
+static scg_sirc_config_t scg_sirc_config = {
 	.enableMode = kSCG_SircEnable,
 	.div2       = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(sircdiv2_clk)),
 #if MHZ(2) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
@@ -66,7 +72,7 @@ ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(fircdiv2_clk),
 		       "Invalid SCG FIRC divider 2 value");
 static const scg_firc_config_t scg_firc_config = {
 	.enableMode = kSCG_FircEnable,
-	.div2       = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv2_clk)), /* b20253 */
+	.div2       = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(fircdiv2_clk)),
 #if MHZ(48) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
 	.range      = kSCG_FircRange48M,
 #elif MHZ(52) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
@@ -81,31 +87,90 @@ static const scg_firc_config_t scg_firc_config = {
 	.trimConfig = NULL
 };
 
-__weak void clk_init(void)
+#if DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk))
+/* System Oscillator (SOSC) configuration */
+ASSERT_ASYNC_CLK_DIV_VALID(SCG_CLOCK_DIV(soscdiv2_clk)),
+			"Invalid SCG SOSC divider 2 value");
+static const scg_sosc_config_t scg_sosc_config = {
+	.freq        = DT_PROP(SCG_CLOCK_NODE(sosc_clk), clock_frequency),
+	.monitorMode = kSCG_SysOscMonitorDisable,
+	.enableMode  = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,
+	.div2        = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(soscdiv2_clk)),
+	.workMode    = DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_mode)
+};
+#endif /* DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq) */
+
+
+static const scg_lpfll_config_t scg_lpfll_config = {
+	.enableMode = kSCG_LpFllEnable,
+	.div2       = TO_ASYNC_CLK_DIV(SCG_CLOCK_DIV(flldiv2_clk)),
+#if MHZ(48) == DT_PROP(SCG_CLOCK_NODE(lpfll_clk), clock_frequency)
+	.range      = kSCG_LpFllRange48M,
+#elif MHZ(72) == DT_PROP(SCG_CLOCK_NODE(lpfll_clk), clock_frequency)
+	.range      = kSCG_LpFllRange72M,
+#elif MHZ(96) == DT_PROP(SCG_CLOCK_NODE(lpfll_clk), clock_frequency)
+	.range      = kSCG_LpFllRange96M,
+#else
+#error Invalid SCG FLL clock frequency
+#endif
+	.trimConfig = NULL,
+};
+
+
+static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
 {
-	const scg_sys_clk_config_t scg_sys_clk_config_safe = {
-		.divSlow = kSCG_SysClkDivBy4,
-		.divCore = kSCG_SysClkDivBy1,
-		.src     = kSCG_SysClkSrcSirc
+	scg_sys_clk_config_t curConfig;
+	const scg_sirc_config_t scgSircConfig       = {.enableMode = kSCG_SircEnable,
+						.div2       = kSCG_AsyncClkDivBy2,
+						.range      = kSCG_SircRangeHigh};
+	scg_sys_clk_config_t sysClkSafeConfigSource = {
+		.divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
+		.divCore = kSCG_SysClkDivBy1, /* Core clock divider */
+		.src     = kSCG_SysClkSrcSirc /* System clock source */
 	};
-	scg_sys_clk_config_t current;
+	/* Init Sirc. */
+	CLOCK_InitSirc(&scgSircConfig);
+	/* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
+	CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
+	/* Wait for clock source switch finished. */
+	do {
+		CLOCK_GetCurSysClkConfig(&curConfig);
+	} while (curConfig.src != sysClkSafeConfigSource.src);
+
+	/* Init Firc. */
+	CLOCK_InitFirc(fircConfig);
+	/* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
+	sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
+	CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
+	/* Wait for clock source switch finished. */
+	do {
+		CLOCK_GetCurSysClkConfig(&curConfig);
+	} while (curConfig.src != sysClkSafeConfigSource.src);
+}
 
-	/* Configure SIRC */
-	CLOCK_InitSirc(&scg_sirc_config);
 
-	/* Temporary switch to safe SIRC in order to configure FIRC */
-	CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config_safe);
-	do {
-		CLOCK_GetCurSysClkConfig(&current);
-	} while (current.src != scg_sys_clk_config_safe.src);
-	CLOCK_InitFirc(&scg_firc_config);
+__weak void clk_init(void)
+{
+	scg_sys_clk_config_t current;
 
-	/* Only RUN mode supported for now */
-	CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config);
+#if DT_NODE_HAS_STATUS_OKAY(SCG_CLOCK_NODE(sosc_clk))
+	/* Init SOSC according to board configuration. */
+	CLOCK_InitSysOsc(&scg_sysosc_config);
+	CLOCK_SetXtal0Freq(scg_sysosc_config.freq);
+#endif
+	/* Init FIRC. */
+	CLOCK_CONFIG_FircSafeConfig(&scg_firc_config);
+	/* Init SIRC. */
+    	CLOCK_InitSirc(&scg_sirc_config);
+    	/* Init LPFLL. */
+    	CLOCK_InitLpFll(&scg_lpfll_config);
+    	/* Finally init the App desired clock */
+    	CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config);
 	do {
-		CLOCK_GetCurSysClkConfig(&current);
+	     CLOCK_GetCurSysClkConfig(&current);
 	} while (current.src != scg_sys_clk_config.src);
 
+
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
 	CLOCK_SetIpSrc(kCLOCK_Lpuart0,
 		       DT_CLOCKS_CELL(DT_NODELABEL(lpuart0), ip_source));