Merge pull request #216 from siliconcompiler/yosys-slang-more

bypass sv2v for all systemverilog designs

Author: gadfort

.gitignore

@@ -5,3 +5,4 @@ gallery/
 _version.py
 .venv/
 .vscode/
+sc_issue*

scgallery/designs/caliptra/datavault.py

@@ -26,7 +26,6 @@ def setup():
 
 def setup_physical(chip):
     chip.set('constraint', 'density', 30)
-
     for task in ('global_placement', 'pin_placement'):
         chip.set('tool', 'openroad', 'task', task, 'var', 'place_density', '0.40')
 

scgallery/designs/cva6/cva6.py

@@ -210,8 +210,8 @@ def setup():
 
 def setup_physical(chip):
     chip.set('tool', 'sv2v', 'task', 'convert', 'var', 'skip_convert', True)
-
     chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'use_slang', True)
+
     chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'flatten', False)
 
     chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'abc_clock_derating', '0.95')

scgallery/designs/fazyrv/fazyrv.py

@@ -52,6 +52,9 @@ def setup():
 
 
 def setup_physical(chip):
+    chip.set('tool', 'sv2v', 'task', 'convert', 'var', 'skip_convert', True)
+    chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'use_slang', True)
+
     chip.set('option', 'define', 'SYNTHESIS')
 
     if chip.get('option', 'pdk') == 'asap7':
@@ -63,7 +66,7 @@ def setup_physical(chip):
     if chip.get('option', 'pdk') == 'ihp130':
         chip.set('constraint', 'aspectratio', 0.25)
         chip.set('tool', 'openroad', 'task', 'macro_placement', 'var', 'macro_place_halo',
-                 [20, 40])
+                 [20, 35])
     if chip.get('option', 'pdk') == 'skywater130':
         chip.set('constraint', 'aspectratio', 0.80)
 

scgallery/designs/ibex/ibex.py

@@ -50,6 +50,9 @@ def setup():
 
 
 def setup_physical(chip):
+    chip.set('tool', 'sv2v', 'task', 'convert', 'var', 'skip_convert', True)
+    chip.set('tool', 'yosys', 'task', 'syn_asic', 'var', 'use_slang', True)
+
     chip.add('option', 'define', 'SYNTHESIS')
 
     if chip.get('option', 'pdk') == 'asap7':