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decadaydecaday
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Add SPI v1 & v2 (f030 f072)
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5 files changed

+858
-7
lines changed

5 files changed

+858
-7
lines changed

‎data/peripherals/F030.yaml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -484,7 +484,7 @@
484484
address: 0x40013000
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registers:
486486
kind: spi
487-
version: common
487+
version: v1
488488
block: SPI
489489
rcc:
490490
bus_clock: PCLK1
@@ -503,7 +503,7 @@
503503
address: 0x40003800
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registers:
505505
kind: spi
506-
version: common
506+
version: v1
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block: SPI
508508
rcc:
509509
bus_clock: PCLK1

‎data/peripherals/F072.yaml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -336,7 +336,7 @@
336336
address: 0x40013000
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registers:
338338
kind: spi
339-
version: common
339+
version: v2
340340
block: SPI
341341
rcc:
342342
bus_clock: PCLK1
@@ -355,7 +355,7 @@
355355
address: 0x40003800
356356
registers:
357357
kind: spi
358-
version: common
358+
version: v2
359359
block: SPI
360360
rcc:
361361
bus_clock: PCLK1

‎data/registers/spi_v1.yaml

Lines changed: 311 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,311 @@
1+
block/SPI:
2+
description: Serial peripheral interface.
3+
items:
4+
- name: CR1
5+
description: control register 1.
6+
byte_offset: 0
7+
fieldset: CR1
8+
- name: CR2
9+
description: control register 2.
10+
byte_offset: 4
11+
fieldset: CR2
12+
- name: SR
13+
description: status register.
14+
byte_offset: 8
15+
fieldset: SR
16+
- name: DR
17+
description: data register.
18+
byte_offset: 12
19+
fieldset: DR
20+
fieldset/CR1:
21+
description: control register 1.
22+
fields:
23+
- name: CPHA
24+
description: Clock phase.
25+
bit_offset: 0
26+
bit_size: 1
27+
enum: CPHA
28+
- name: CPOL
29+
description: Clock polarity.
30+
bit_offset: 1
31+
bit_size: 1
32+
enum: CPOL
33+
- name: MSTR
34+
description: Master selection.
35+
bit_offset: 2
36+
bit_size: 1
37+
enum: MSTR
38+
- name: BR
39+
description: Baud rate control.
40+
bit_offset: 3
41+
bit_size: 3
42+
enum: BR
43+
- name: SPE
44+
description: SPI enable.
45+
bit_offset: 6
46+
bit_size: 1
47+
- name: LSBFIRST
48+
description: Frame format.
49+
bit_offset: 7
50+
bit_size: 1
51+
enum: LSBFIRST
52+
- name: SSI
53+
description: Internal slave select.
54+
bit_offset: 8
55+
bit_size: 1
56+
- name: SSM
57+
description: Software slave management.
58+
bit_offset: 9
59+
bit_size: 1
60+
- name: RXONLY
61+
description: Receive only.
62+
bit_offset: 10
63+
bit_size: 1
64+
enum: RXONLY
65+
- name: BIDIOE
66+
description: Select the direction of transfer in bidirectional mode.
67+
bit_offset: 14
68+
bit_size: 1
69+
enum: BIDIOE
70+
- name: BIDIMODE
71+
description: Bidirectional data mode enable.
72+
bit_offset: 15
73+
bit_size: 1
74+
enum: BIDIMODE
75+
fieldset/CR2:
76+
description: control register 2.
77+
fields:
78+
- name: RXDMAEN
79+
description: Rx buffer DMA enable.
80+
bit_offset: 0
81+
bit_size: 1
82+
- name: TXDMAEN
83+
description: Tx buffer DMA enable.
84+
bit_offset: 1
85+
bit_size: 1
86+
- name: SSOE
87+
description: SS output enable.
88+
bit_offset: 2
89+
bit_size: 1
90+
- name: ERRIE
91+
description: Error interrupt enable.
92+
bit_offset: 5
93+
bit_size: 1
94+
- name: RXNEIE
95+
description: RX buffer not empty interrupt enable.
96+
bit_offset: 6
97+
bit_size: 1
98+
- name: TXEIE
99+
description: Tx buffer empty interrupt enable.
100+
bit_offset: 7
101+
bit_size: 1
102+
- name: DS
103+
description: Data length.
104+
bit_offset: 11
105+
bit_size: 1
106+
- name: FRXTH
107+
description: FIFO reception threshold.
108+
bit_offset: 12
109+
bit_size: 1
110+
enum: FRXTH
111+
- name: LDMA_RX
112+
description: Last DMA transfer for reception.
113+
bit_offset: 13
114+
bit_size: 1
115+
enum: LDMA_RX
116+
- name: LDMA_TX
117+
description: Last DMA transfer for transmission.
118+
bit_offset: 14
119+
bit_size: 1
120+
enum: LDMA_TX
121+
- name: SLVFM
122+
description: Slave fast mode enable.
123+
bit_offset: 15
124+
bit_size: 1
125+
fieldset/DR:
126+
description: data register.
127+
fields:
128+
- name: DR
129+
description: Data register.
130+
bit_offset: 0
131+
bit_size: 16
132+
fieldset/SR:
133+
description: status register.
134+
fields:
135+
- name: RXNE
136+
description: Receive buffer not empty.
137+
bit_offset: 0
138+
bit_size: 1
139+
- name: TXE
140+
description: Transmit buffer empty.
141+
bit_offset: 1
142+
bit_size: 1
143+
- name: MODF
144+
description: Mode fault.
145+
bit_offset: 5
146+
bit_size: 1
147+
- name: OVR
148+
description: Overrun flag.
149+
bit_offset: 6
150+
bit_size: 1
151+
- name: BSY
152+
description: Busy flag.
153+
bit_offset: 7
154+
bit_size: 1
155+
- name: FRLVL
156+
description: FIFO reception level.
157+
bit_offset: 9
158+
bit_size: 2
159+
enum: FRLVL
160+
- name: FTLVL
161+
description: FIFO Transmission Level.
162+
bit_offset: 11
163+
bit_size: 2
164+
enum: FTLVL
165+
enum/BIDIMODE:
166+
bit_size: 1
167+
variants:
168+
- name: Unidirectional
169+
description: 2-line unidirectional data mode selected
170+
value: 0
171+
- name: Bidirectional
172+
description: 1-line bidirectional data mode selected
173+
value: 1
174+
enum/BIDIOE:
175+
bit_size: 1
176+
variants:
177+
- name: Receive
178+
description: Output disabled (receive-only mode)
179+
value: 0
180+
- name: Transmit
181+
description: Output enabled (transmit-only mode)
182+
value: 1
183+
enum/BR:
184+
bit_size: 3
185+
variants:
186+
- name: Div2
187+
description: f_PCLK / 2
188+
value: 0
189+
- name: Div4
190+
description: f_PCLK / 4
191+
value: 1
192+
- name: Div8
193+
description: f_PCLK / 8
194+
value: 2
195+
- name: Div16
196+
description: f_PCLK / 16
197+
value: 3
198+
- name: Div32
199+
description: f_PCLK / 32
200+
value: 4
201+
- name: Div64
202+
description: f_PCLK / 64
203+
value: 5
204+
- name: Div128
205+
description: f_PCLK / 128
206+
value: 6
207+
- name: Div256
208+
description: f_PCLK / 256
209+
value: 7
210+
enum/CPHA:
211+
bit_size: 1
212+
variants:
213+
- name: FirstEdge
214+
description: The first clock transition is the first data capture edge
215+
value: 0
216+
- name: SecondEdge
217+
description: The second clock transition is the first data capture edge
218+
value: 1
219+
enum/CPOL:
220+
bit_size: 1
221+
variants:
222+
- name: IdleLow
223+
description: CK to 0 when idle
224+
value: 0
225+
- name: IdleHigh
226+
description: CK to 1 when idle
227+
value: 1
228+
enum/FRLVL:
229+
bit_size: 2
230+
variants:
231+
- name: Empty
232+
description: Rx FIFO Empty
233+
value: 0
234+
- name: Quarter
235+
description: Rx 1/4 FIFO
236+
value: 1
237+
- name: Half
238+
description: Rx 1/2 FIFO
239+
value: 2
240+
- name: Full
241+
description: Rx FIFO full
242+
value: 3
243+
enum/FRXTH:
244+
bit_size: 1
245+
variants:
246+
- name: Half
247+
description: RXNE event is generated if the FIFO level is greater than or equal to 1/2 (16-bit)
248+
value: 0
249+
- name: Quarter
250+
description: RXNE event is generated if the FIFO level is greater than or equal to 1/4 (8-bit)
251+
value: 1
252+
enum/FTLVL:
253+
bit_size: 2
254+
variants:
255+
- name: Empty
256+
description: Tx FIFO Empty
257+
value: 0
258+
- name: Quarter
259+
description: Tx 1/4 FIFO
260+
value: 1
261+
- name: Half
262+
description: Tx 1/2 FIFO
263+
value: 2
264+
- name: Full
265+
description: Tx FIFO full
266+
value: 3
267+
enum/LDMA_RX:
268+
bit_size: 1
269+
variants:
270+
- name: Even
271+
description: Number of data to transfer for receive is even
272+
value: 0
273+
- name: Odd
274+
description: Number of data to transfer for receive is odd
275+
value: 1
276+
enum/LDMA_TX:
277+
bit_size: 1
278+
variants:
279+
- name: Even
280+
description: Number of data to transfer for transmit is even
281+
value: 0
282+
- name: Odd
283+
description: Number of data to transfer for transmit is odd
284+
value: 1
285+
enum/LSBFIRST:
286+
bit_size: 1
287+
variants:
288+
- name: MSBFirst
289+
description: Data is transmitted/received with the MSB first
290+
value: 0
291+
- name: LSBFirst
292+
description: Data is transmitted/received with the LSB first
293+
value: 1
294+
enum/MSTR:
295+
bit_size: 1
296+
variants:
297+
- name: Slave
298+
description: Slave configuration
299+
value: 0
300+
- name: Master
301+
description: Master configuration
302+
value: 1
303+
enum/RXONLY:
304+
bit_size: 1
305+
variants:
306+
- name: FullDuplex
307+
description: Full duplex (Transmit and receive)
308+
value: 0
309+
- name: OutputDisabled
310+
description: Output disabled (Receive-only mode)
311+
value: 1

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