Merge pull request #20 from decaday/feat/dma2

DMA & SYSCFG

Author: decaday

README.md

@@ -49,9 +49,7 @@ Date: 20240312
 
 - Configure the additional registers for peripherals like USART and I2C on the PY32F072, which has more registers compared to version 1 (F030).
 
-- Set up configurations for cut-down variants such as PY32F003, PY32F002A, and PY32F040.
-
-- Extend USB `FRAMENUM` and `OUTCOUNT` Fields to 11 bits.
+- Set up configurations for cut-down variants such as PY32F003, PY32F002A, PY32F040.
 
 ## Contirbute
 

data/af/PY32F030.yaml

@@ -543,7 +543,7 @@ USART2:
   - af: 4
     pin: PF3
     signal: TX
-ADC:
+ADC1:
   - pin: PA0
     signal: IN0
   - pin: PA1

data/af/PY32F07X.yaml

@@ -778,7 +778,7 @@ USART4:
   - af: 0
     pin: PC12
     signal: CK
-ADC:
+ADC1:
   - pin: PA0
     signal: IN0
   - pin: PA1

data/chips/PY32F030F16.yaml

@@ -50,7 +50,10 @@ cores:
     include_peripherals:
       - "../peripherals/F030.yaml"
     include_afs: "../af/PY32F030.yaml"
-    dma_channels:
+    include_dma_channels:
+      DMA1_CH1: "../dma_channels/PY32F030.yaml"
+      DMA1_CH2: "../dma_channels/PY32F030.yaml"
+      DMA1_CH3: "../dma_channels/PY32F030.yaml"
 _raw:
   12bitADCUnitsCHs: 1(2+2)
   12bitDACUnitsCHs: '-'

data/chips/PY32F030K28.yaml

@@ -51,7 +51,10 @@ cores:
     include_peripherals:
       - "../peripherals/F030.yaml"
     include_afs: "../af/PY32F030.yaml"
-    dma_channels:
+    include_dma_channels:
+      DMA1_CH1: "../dma_channels/PY32F030.yaml"
+      DMA1_CH2: "../dma_channels/PY32F030.yaml"
+      DMA1_CH3: "../dma_channels/PY32F030.yaml"
 _raw:
   12bitADCUnitsCHs: 1(10+2)
   12bitDACUnitsCHs: '-'

data/chips/PY32F072C1B.yaml

@@ -57,7 +57,14 @@ cores:
     include_peripherals:
       - "../peripherals/F072.yaml"
     include_afs: "../af/PY32F07X.yaml"
-    dma_channels:
+    include_dma_channels: 
+      DMA1_CH1: "../dma_channels/PY32F072.yaml"
+      DMA1_CH2: "../dma_channels/PY32F072.yaml"
+      DMA1_CH3: "../dma_channels/PY32F072.yaml"
+      DMA1_CH4: "../dma_channels/PY32F072.yaml"
+      DMA1_CH5: "../dma_channels/PY32F072.yaml"
+      DMA1_CH6: "../dma_channels/PY32F072.yaml"
+      DMA1_CH7: "../dma_channels/PY32F072.yaml"
 _raw:
   12bitADCUnitsCHs: 1(13+8)
   12bitDACUnitsCHs: 1(2)

data/dma_channels/PY32F030.yaml

@@ -0,0 +1,27 @@
+ADC1: 0
+SPI1_TX: 1
+SPI1_RX: 2
+SPI2_TX: 3
+SPI2_RX: 4
+USART1_TX: 5
+USART1_RX: 6
+USART2_TX: 7
+USART2_RX: 8
+I2C1_TX: 9
+I2C1_RX: 10
+TIM1_CH1: 11
+TIM1_CH2: 12
+TIM1_CH3: 13
+TIM1_CH4: 14
+TIM1_COM: 15
+TIM1_UP: 16
+TIM1_TRIG: 17
+TIM3_CH1: 18
+TIM3_CH3: 19
+TIM3_CH4: 20
+TIM3_TRG: 21
+TIM3_UP: 22
+TIM16_CH1: 24
+TIM16_UP: 25
+TIM17_CH1: 26
+TIM17_UP: 27

data/dma_channels/PY32F072.yaml

@@ -0,0 +1,51 @@
+ADC1: 0
+DAC1: 1
+DAC2: 2
+SPI1_RX: 3
+SPI1_TX: 4
+SPI2_RX: 5
+SPI2_TX: 6
+USART1_RX: 7
+USART1_TX: 8
+USART2_RX: 9
+USART2_TX: 10
+USART3_RX: 11
+USART3_TX: 12
+USART4_RX: 13
+USART4_TX: 14
+I2C1_RX: 15
+I2C1_TX: 16
+I2C2_RX: 17
+I2C2_TX: 18
+TIM1_CH1: 19
+TIM1_CH2: 20
+TIM1_CH3: 21
+TIM1_CH4: 22
+TIM1_COM: 23
+TIM1_TRIG: 24
+TIM1_UP: 25
+TIM2_CH1: 26
+TIM2_CH2: 27
+TIM2_CH3: 28
+TIM2_CH4: 29
+TIM2_UP: 30
+TIM2_TRG: 31
+TIM3_CH1: 32
+TIM3_CH2: 33
+TIM3_CH3: 34
+TIM3_CH4: 35
+TIM3_UP: 36
+TIM3_TRIG: 37
+TIM6_UP: 38
+TIM7_UP: 39
+TIM15_CH1: 40
+TIM15_CH2: 41
+TIM15_UP: 42
+TIM15_TRIG: 43
+TIM15_COM: 44
+TIM16_CH1: 45
+TIM16_UP: 46
+TIM17_CH1: 47
+TIM17_UP: 48
+USB: 49
+LCD: 50

data/dma_channels/PY32F403.yaml

@@ -0,0 +1,67 @@
+ADC1: 0
+ADC2: 1  
+ADC3: 2
+SPI1_RX: 5
+SPI1_TX: 6
+SPI2_RX: 7
+SPI2_TX: 8
+SPI3_RX: 9
+SPI3_TX: 10
+USART1_RX: 11
+USART1_TX: 12
+USART2_RX: 13
+USART2_TX: 14
+USART3_RX: 15
+USART3_TX: 16
+USART4_RX: 17
+USART4_TX: 18
+USART5_RX: 19
+USART5_TX: 20
+I2C1_RX: 21
+I2C1_TX: 22
+I2C2_RX: 23
+I2C2_TX: 24
+TIM1_CH1: 25
+TIM1_CH2: 26
+TIM1_CH3: 27
+TIM1_CH4: 28
+TIM1_COM: 29
+TIM1_TRIG: 30
+TIM1_UP: 31
+TIM2_CH1: 32
+TIM2_CH2: 33
+TIM2_CH3: 34
+TIM2_CH4: 35
+TIM2_UP: 36
+TIM3_CH1: 37
+TIM3_CH3: 38
+TIM3_CH4: 39
+TIM3_UP: 40
+TIM3_TRIG: 41
+TIM4_CH1: 42
+TIM4_CH2: 43
+TIM4_CH3: 44
+TIM4_UP: 45
+TIM5_CH1: 46
+TIM5_CH2: 47
+TIM5_CH3: 48
+TIM5_CH4: 49
+TIM5_UP: 50
+TIM5_TRIG: 51
+TIM6: 52
+TIM7: 53
+TIM8_CH1: 54
+TIM8_CH2: 55
+TIM8_CH3: 56
+TIM8_CH4: 57
+TIM8_COM: 58
+TIM8_TRIG: 59
+TIM8_UP: 60
+TIM2_TRIG: 61
+TIM3_CH2: 62
+TIM4_CH4: 63
+TIM4_TRIG: 64
+ESMC_TX: 65
+ESMC_RX: 66
+SDIO: 67
+USB: 68

data/peripherals/F030.yaml

@@ -1,4 +1,4 @@
-- name: ADC
+- name: ADC1
   address: 0x40012400
   registers:
     kind: adc
@@ -387,25 +387,7 @@
     kind: timer
     version: v1
     block: TIM_1CH_CMP
-  dma_channels:
-    - signal: CH1
-      channel: DMA1_CH1
-      request: 7
-    - signal: UP
-      channel: DMA1_CH1
-      request: 7
-    - signal: CH1
-      channel: DMA1_CH2
-      request: 7
-    - signal: UP
-      channel: DMA1_CH2
-      request: 7
-    - signal: CH1
-      channel: DMA1_CH7
-      request: 7
-    - signal: UP
-      channel: DMA1_CH7
-      request: 7
+    
   rcc:
     bus_clock: PCLK1_TIM
     kernel_clock: PCLK1_TIM
@@ -431,7 +413,7 @@
   address: 0x40010000
   registers:
     kind: syscfg
-    version: common
+    version: f030
     block: SYSCFG
   rcc:
     bus_clock: PCLK1
@@ -443,26 +425,28 @@
       register: APBRSTR2
       field: SYSCFGRST
 
-- name: DMA
+- name: DMA1
   address: 0x40020000
   registers:
     kind: dma
-    version: common
+    version: f030
     block: DMA
   rcc:
-    bus_clock: PCLK1
-    kernel_clock: PCLK1
+    bus_clock: HCLK1
+    kernel_clock: HCLK1
     enable:
       register: AHBENR
       field: DMAEN
     reset:
       register: AHBRSTR
       field: DMARST
   interrupts:
-    - signal: GLOBAL
-      interrupt: DMA_Channel1
-    - signal: GLOBAL
-      interrupt: DMA_Channel2_3
+  - signal: CH1
+    interrupt: DMA_Channel1
+  - signal: CH2
+    interrupt: DMA_Channel2_3
+  - signal: CH3
+    interrupt: DMA_Channel2_3
 
 - name: FLASH
   address: 0x40022000