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ad485x_fmcz: Add 3 wire spi support
1 parent c674ea9 commit e27de65

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3 files changed

+268
-4
lines changed

3 files changed

+268
-4
lines changed

‎projects/ad485x_fmcz/zed/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ M_DEPS += ../../scripts/adi_pd.tcl
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M_DEPS += ../../common/zed/zed_system_constr.xdc
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M_DEPS += ../../common/zed/zed_system_bd.tcl
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M_DEPS += ../../../library/common/ad_iobuf.v
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M_DEPS += ../../../library/common/ad_3w_spi.v
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LIB_DEPS += axi_ad485x
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LIB_DEPS += axi_clkgen

‎projects/ad485x_fmcz/zed/system_project.tcl

Lines changed: 20 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,13 @@ if [info exists ::env(LVDS_CMOS_N)] {
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set env(LVDS_CMOS_N) $LVDS_CMOS_N
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}
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set THREE_W_SPI 0
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if [info exists ::env(THREE_W_SPI)] {
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set THREE_W_SPI $::env(THREE_W_SPI)
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} else {
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set env(THREE_W_SPI) $THREE_W_SPI
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}
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1926
set DEVICE "AD4858"
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if [info exists ::env(DEVICE)] {
2128
set DEVICE $::env(DEVICE)
@@ -26,6 +33,7 @@ if [info exists ::env(DEVICE)] {
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adi_project ad485x_fmcz_zed 0 [list \
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LVDS_CMOS_N $LVDS_CMOS_N \
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DEVICE $DEVICE \
36+
THREE_W_SPI $THREE_W_SPI \
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]
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3139
if {$LVDS_CMOS_N == "0"} {
@@ -42,15 +50,23 @@ if {$LVDS_CMOS_N == "0"} {
4250
]
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}
4452
} else {
45-
adi_project_files {} [list \
46-
"system_top_lvds.v" \
47-
"system_constr_lvds.xdc" \
48-
]
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if {$THREE_W_SPI == "0"} {
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adi_project_files {} [list \
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"system_top_lvds.v" \
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"system_constr_lvds.xdc" \
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]
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} else {
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adi_project_files {} [list \
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"system_top_lvds_3w_spi.v" \
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"system_constr_lvds.xdc" \
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]
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}
4964
}
5065

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adi_project_files {} [list \
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"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
69+
"$ad_hdl_dir/library/common/ad_3w_spi.v" \
5470
]
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adi_project_run ad485x_fmcz_zed

‎projects/ad485x_fmcz/zed/system_top_lvds_3w_spi.v

Lines changed: 247 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,247 @@
1+
// ***************************************************************************
2+
// ***************************************************************************
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// Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
7+
// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
11+
// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
21+
// Free Software Foundation, which can be found in the top level directory
22+
// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
27+
// 2. An ADI specific BSD license, which can be found in the top level directory
28+
// of this repository (LICENSE_ADIBSD), and also on-line at:
29+
// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
30+
// This will allow to generate bit files and not release the source code,
31+
// as long as it attaches to an ADI device.
32+
//
33+
// ***************************************************************************
34+
// ***************************************************************************
35+
36+
`timescale 1ns/100ps
37+
38+
module system_top (
39+
inout [14:0] ddr_addr,
40+
inout [ 2:0] ddr_ba,
41+
inout ddr_cas_n,
42+
inout ddr_ck_n,
43+
inout ddr_ck_p,
44+
inout ddr_cke,
45+
inout ddr_cs_n,
46+
inout [ 3:0] ddr_dm,
47+
inout [31:0] ddr_dq,
48+
inout [ 3:0] ddr_dqs_n,
49+
inout [ 3:0] ddr_dqs_p,
50+
inout ddr_odt,
51+
inout ddr_ras_n,
52+
inout ddr_reset_n,
53+
inout ddr_we_n,
54+
55+
inout fixed_io_ddr_vrn,
56+
inout fixed_io_ddr_vrp,
57+
inout [53:0] fixed_io_mio,
58+
inout fixed_io_ps_clk,
59+
inout fixed_io_ps_porb,
60+
inout fixed_io_ps_srstb,
61+
62+
inout [31:0] gpio_bd,
63+
64+
output hdmi_out_clk,
65+
output hdmi_vsync,
66+
output hdmi_hsync,
67+
output hdmi_data_e,
68+
output [15:0] hdmi_data,
69+
70+
output i2s_mclk,
71+
output i2s_bclk,
72+
output i2s_lrclk,
73+
output i2s_sdata_out,
74+
input i2s_sdata_in,
75+
76+
output spdif,
77+
78+
inout iic_scl,
79+
inout iic_sda,
80+
inout [ 1:0] iic_mux_scl,
81+
inout [ 1:0] iic_mux_sda,
82+
83+
input otg_vbusoc,
84+
85+
output scki_p,
86+
output scki_n,
87+
input scko_p,
88+
input scko_n,
89+
input sdo_p,
90+
input sdo_n,
91+
92+
input busy,
93+
output cnv,
94+
output pd,
95+
output lvds_cmos_n,
96+
97+
output reg csck, //spiad_sck
98+
inout csdio,//spiad_sdi
99+
output reg cs_n //spiad_csn
100+
);
101+
102+
// internal signals
103+
104+
wire [63:0] gpio_i;
105+
wire [63:0] gpio_o;
106+
wire [63:0] gpio_t;
107+
wire [ 1:0] iic_mux_scl_i_s;
108+
wire [ 1:0] iic_mux_scl_o_s;
109+
wire iic_mux_scl_t_s;
110+
wire [ 1:0] iic_mux_sda_i_s;
111+
wire [ 1:0] iic_mux_sda_o_s;
112+
wire iic_mux_sda_t_s;
113+
114+
assign gpio_i[63:32] = gpio_o[63:32];
115+
assign pd = gpio_o[32];
116+
117+
wire spiad_sck_s;
118+
wire spiad_csn_s;
119+
wire miso_s;
120+
wire mosi_s;
121+
reg [ 4:0] cnt_cs_up = 3'd0;
122+
123+
always @(posedge cpu_clk) begin
124+
csck <= spiad_sck_s;
125+
if (spiad_csn_s == 1'b0) begin
126+
cs_n <= 1'b0;
127+
cnt_cs_up <= 3'd0;
128+
end else if (cnt_cs_up == 5'h1f) begin
129+
cs_n <= 1'b0;
130+
cnt_cs_up <= cnt_cs_up;
131+
end else begin
132+
cs_n <= 1'b1;
133+
cnt_cs_up <= cnt_cs_up + 3'd1;
134+
end
135+
end
136+
137+
// instantiations
138+
139+
ad_3w_spi #(
140+
.NUM_OF_SLAVES(2)
141+
) i_spi (
142+
.spi_csn(spiad_csn_s),
143+
.spi_clk(csck),
144+
.spi_mosi(mosi_s),
145+
.spi_miso(miso_s),
146+
.spi_sdio(csdio),
147+
.spi_dir());
148+
149+
ad_iobuf #(
150+
.DATA_WIDTH(32)
151+
) i_iobuf (
152+
.dio_t(gpio_t[31:0]),
153+
.dio_i(gpio_o[31:0]),
154+
.dio_o(gpio_i[31:0]),
155+
.dio_p(gpio_bd));
156+
157+
ad_iobuf #(
158+
.DATA_WIDTH(2)
159+
) i_iic_mux_scl (
160+
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
161+
.dio_i(iic_mux_scl_o_s),
162+
.dio_o(iic_mux_scl_i_s),
163+
.dio_p(iic_mux_scl));
164+
165+
ad_iobuf #(
166+
.DATA_WIDTH(2)
167+
) i_iic_mux_sda (
168+
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
169+
.dio_i(iic_mux_sda_o_s),
170+
.dio_o(iic_mux_sda_i_s),
171+
.dio_p(iic_mux_sda));
172+
173+
system_wrapper i_system_wrapper (
174+
.ddr_addr (ddr_addr),
175+
.ddr_ba (ddr_ba),
176+
.ddr_cas_n (ddr_cas_n),
177+
.ddr_ck_n (ddr_ck_n),
178+
.ddr_ck_p (ddr_ck_p),
179+
.ddr_cke (ddr_cke),
180+
.ddr_cs_n (ddr_cs_n),
181+
.ddr_dm (ddr_dm),
182+
.ddr_dq (ddr_dq),
183+
.ddr_dqs_n (ddr_dqs_n),
184+
.ddr_dqs_p (ddr_dqs_p),
185+
.ddr_odt (ddr_odt),
186+
.ddr_ras_n (ddr_ras_n),
187+
.ddr_reset_n (ddr_reset_n),
188+
.ddr_we_n (ddr_we_n),
189+
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
190+
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
191+
.fixed_io_mio (fixed_io_mio),
192+
.fixed_io_ps_clk (fixed_io_ps_clk),
193+
.fixed_io_ps_porb (fixed_io_ps_porb),
194+
.fixed_io_ps_srstb (fixed_io_ps_srstb),
195+
.gpio_i (gpio_i),
196+
.gpio_o (gpio_o),
197+
.gpio_t (gpio_t),
198+
.hdmi_data (hdmi_data),
199+
.hdmi_data_e (hdmi_data_e),
200+
.hdmi_hsync (hdmi_hsync),
201+
.hdmi_out_clk (hdmi_out_clk),
202+
.hdmi_vsync (hdmi_vsync),
203+
.i2s_bclk (i2s_bclk),
204+
.i2s_lrclk (i2s_lrclk),
205+
.i2s_mclk (i2s_mclk),
206+
.i2s_sdata_in (i2s_sdata_in),
207+
.i2s_sdata_out (i2s_sdata_out),
208+
.iic_fmc_scl_io (iic_scl),
209+
.iic_fmc_sda_io (iic_sda),
210+
.iic_mux_scl_i (iic_mux_scl_i_s),
211+
.iic_mux_scl_o (iic_mux_scl_o_s),
212+
.iic_mux_scl_t (iic_mux_scl_t_s),
213+
.iic_mux_sda_i (iic_mux_sda_i_s),
214+
.iic_mux_sda_o (iic_mux_sda_o_s),
215+
.iic_mux_sda_t (iic_mux_sda_t_s),
216+
.otg_vbusoc (otg_vbusoc),
217+
.spdif (spdif),
218+
.system_cpu_clk (cpu_clk),
219+
.spi0_clk_i (spiad_sck_s),
220+
.spi0_clk_o (spiad_sck_s),
221+
.spi0_csn_0_o (spiad_csn_s),
222+
.spi0_csn_1_o (),
223+
.spi0_csn_2_o (),
224+
.spi0_csn_i (1'b1),
225+
.spi0_sdi_i (miso_s),
226+
.spi0_sdo_i (mosi_s),
227+
.spi0_sdo_o (mosi_s),
228+
.spi1_clk_i (1'b0),
229+
.spi1_clk_o (),
230+
.spi1_csn_0_o (),
231+
.spi1_csn_1_o (),
232+
.spi1_csn_2_o (),
233+
.spi1_csn_i (1'b1),
234+
.spi1_sdi_i (1'b0),
235+
.spi1_sdo_i (1'b0),
236+
.spi1_sdo_o (),
237+
.scki_p (scki_p),
238+
.scki_n (scki_n),
239+
.scko_p (scko_p),
240+
.scko_n (scko_n),
241+
.sdo_p (sdo_p),
242+
.sdo_n (sdo_n),
243+
.busy (busy),
244+
.cnv (cnv),
245+
.lvds_cmos_n (lvds_cmos_n));
246+
247+
endmodule

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