@@ -18,17 +18,17 @@ native
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// push PC
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value = simcore_native_get_value("CPU", "REG_PC") ;
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- var reg_sp = simcore_native_get_value("BR ", 29 ) ;
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+ var reg_sp = simcore_native_get_value("CPU ", "BR.29" ) ;
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reg_sp = reg_sp - 4 ;
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simcore_native_set_value("MEMORY", reg_sp, value) ;
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- simcore_native_set_value("BR ", 29 , reg_sp) ;
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+ simcore_native_set_value("CPU ", "BR.29" , reg_sp) ;
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// push SR
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value = simcore_native_get_value("CPU", "REG_SR") ;
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- reg_sp = simcore_native_get_value("BR ", 29 ) ;
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+ reg_sp = simcore_native_get_value("CPU ", "BR.29" ) ;
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reg_sp = reg_sp - 4 ;
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simcore_native_set_value("MEMORY", reg_sp, value) ;
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- simcore_native_set_value("BR ", 29 , reg_sp) ;
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+ simcore_native_set_value("CPU ", "BR.29" , reg_sp) ;
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// MAR <- RT1*4
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var addr = simcore_native_get_value("CPU", "REG_RT1") ;
@@ -64,18 +64,18 @@ sret {
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native,
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{
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// pop SR
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- var reg_sp = simcore_native_get_value("BR ", 29 ) ;
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+ var reg_sp = simcore_native_get_value("CPU ", "BR.29" ) ;
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var value = simcore_native_get_value("MEMORY", reg_sp) ;
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reg_sp = reg_sp + 4 ;
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simcore_native_set_value("CPU", "REG_SR", value) ;
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- simcore_native_set_value("BR ", 29 , reg_sp) ;
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+ simcore_native_set_value("CPU ", "BR.29" , reg_sp) ;
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// pop PC
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- var reg_sp = simcore_native_get_value("BR ", 29 ) ;
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+ var reg_sp = simcore_native_get_value("CPU ", "BR.29" ) ;
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var value = simcore_native_get_value("MEMORY", reg_sp) ;
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reg_sp = reg_sp + 4 ;
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simcore_native_set_value("CPU", "REG_PC", value) ;
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- simcore_native_set_value("BR ", 29 , reg_sp) ;
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+ simcore_native_set_value("CPU ", "BR.29" , reg_sp) ;
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simcore_native_go_maddr(0) ;
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}
@@ -90,17 +90,17 @@ ecall {
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// push PC
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var value = simcore_native_get_value("CPU", "REG_PC") ;
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- var reg_sp = simcore_native_get_value("BR ", 29 ) ;
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+ var reg_sp = simcore_native_get_value("CPU ", "BR.29" ) ;
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reg_sp = reg_sp - 4 ;
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simcore_native_set_value("MEMORY", reg_sp, value) ;
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- simcore_native_set_value("BR ", 29 , reg_sp) ;
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+ simcore_native_set_value("CPU ", "BR.29" , reg_sp) ;
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// push SR
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value = simcore_native_get_value("CPU", "REG_SR") ;
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- reg_sp = simcore_native_get_value("BR ", 29 ) ;
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+ reg_sp = simcore_native_get_value("CPU ", "BR.29" ) ;
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reg_sp = reg_sp - 4 ;
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simcore_native_set_value("MEMORY", reg_sp, value) ;
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- simcore_native_set_value("BR ", 29 , reg_sp) ;
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+ simcore_native_set_value("CPU ", "BR.29" , reg_sp) ;
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// MAR <- RT1*4
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var addr = simcore_native_get_value("CPU", "REG_RT1") ;
@@ -134,7 +134,7 @@ in reg val {
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var addr = simcore_native_get_field_from_ir(fields, 1) ;
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var value = simcore_native_get_value("DEVICE", addr) ;
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- simcore_native_set_value("BR", reg1, value) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, value) ;
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simcore_native_go_maddr(0) ;
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}
@@ -152,7 +152,7 @@ out reg val {
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var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
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var addr = simcore_native_get_field_from_ir(fields, 1) ;
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- var value = simcore_native_get_value("BR", reg1) ;
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+ var value = simcore_native_get_value("CPU", "BR." + reg1) ;
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simcore_native_set_value("DEVICE", addr, value) ;
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simcore_native_go_maddr(0) ;
@@ -176,15 +176,15 @@ lb rd (rs1) {
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var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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- var b_addr = simcore_native_get_value("BR", reg2) ;
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+ var b_addr = simcore_native_get_value("CPU", "BR." + reg2) ;
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var w_addr = b_addr & 0xFFFFFFFC ;
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var w_value = simcore_native_get_value("MEMORY", w_addr) ;
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var b_value = b_addr & 0x00000003 ;
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b_value = w_value >>> (8 * b_value) ;
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if (b_value & 0x00000080)
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b_value = b_value | 0xFFFFFF00 ;
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else b_value = b_value & 0x000000FF ;
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- simcore_native_set_value("BR", reg1, b_value) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, b_value) ;
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simcore_native_go_maddr(0) ;
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}
@@ -202,8 +202,8 @@ sb rs2 (rs1) {
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var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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- var b_addr = simcore_native_get_value("BR", reg2) ;
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- var b_value = simcore_native_get_value("BR", reg1) ;
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+ var b_addr = simcore_native_get_value("CPU", "BR." + reg2) ;
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+ var b_value = simcore_native_get_value("CPU", "BR." + reg1) ;
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b_value = b_value & 0x000000FF ;
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var w_addr = b_addr & 0xFFFFFFFC ;
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var w_value = simcore_native_get_value("MEMORY", w_addr) ;
@@ -236,8 +236,8 @@ mul reg1 reg2 reg3 {
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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var reg3 = simcore_native_get_field_from_ir(fields, 2) ;
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- var result = simcore_native_get_value("BR ", reg2) * simcore_native_get_value("BR", reg3) ;
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- simcore_native_set_value("BR", reg1, result) ;
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+ var result = simcore_native_get_value("CPU ", "BR." + reg2) * simcore_native_get_value("CPU", "BR." + reg3) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, result) ;
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simcore_native_go_maddr(0) ;
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}
@@ -257,8 +257,8 @@ rem reg1 reg2 reg3 {
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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var reg3 = simcore_native_get_field_from_ir(fields, 2) ;
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- var result = simcore_native_get_value("BR ", reg2) % simcore_native_get_value("BR", reg3) ;
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- simcore_native_set_value("BR", reg1, result) ;
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+ var result = simcore_native_get_value("CPU ", "BR." + reg2) % simcore_native_get_value("CPU", "BR." + reg3) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, result) ;
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simcore_native_go_maddr(0) ;
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}
@@ -278,10 +278,10 @@ div reg1 reg2 reg3 {
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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var reg3 = simcore_native_get_field_from_ir(fields, 2) ;
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- if (simcore_native_get_value("BR", reg3) != 0)
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+ if (simcore_native_get_value("CPU", "BR." + reg3) != 0)
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{
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- var result = simcore_native_get_value("BR ", reg2) / simcore_native_get_value("BR", reg3) ;
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- simcore_native_set_value("BR", reg1, result) ;
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+ var result = simcore_native_get_value("CPU ", "BR." + reg2) / simcore_native_get_value("CPU", "BR." + reg3) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, result) ;
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simcore_native_go_maddr(0) ;
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return ;
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}
@@ -290,17 +290,17 @@ div reg1 reg2 reg3 {
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// push PC
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var value = simcore_native_get_value (" CPU" , " REG_PC" ) ;
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- var reg_sp = simcore_native_get_value (" BR " , 29 ) ;
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+ var reg_sp = simcore_native_get_value (" CPU " , " BR.29 " ) ;
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reg_sp = reg_sp - 4 ;
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simcore_native_set_value (" MEMORY" , reg_sp , value ) ;
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- simcore_native_set_value (" BR " , 29 , reg_sp ) ;
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+ simcore_native_set_value (" CPU " , " BR.29 " , reg_sp ) ;
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// push SR
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value = simcore_native_get_value (" CPU" , " REG_SR" ) ;
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- reg_sp = simcore_native_get_value (" BR " , 29 ) ;
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+ reg_sp = simcore_native_get_value (" CPU " , " BR.29 " ) ;
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reg_sp = reg_sp - 4 ;
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simcore_native_set_value (" MEMORY" , reg_sp , value ) ;
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- simcore_native_set_value (" BR " , 29 , reg_sp ) ;
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+ simcore_native_set_value (" CPU " , " BR.29 " , reg_sp ) ;
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// MAR <- RT1*4
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var addr = simcore_native_get_value (" CPU" , " REG_RT1" ) ;
@@ -334,8 +334,8 @@ bge rs1 rs2 offset {
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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var offset = simcore_native_get_field_from_ir(fields, 2) ;
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- reg1 = simcore_native_get_value("BR", reg1) ;
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- reg2 = simcore_native_get_value("BR", reg2) ;
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+ reg1 = simcore_native_get_value("CPU", "BR." + reg1) ;
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+ reg2 = simcore_native_get_value("CPU", "BR." + reg2) ;
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if (reg1 >= reg2)
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{
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var pc = simcore_native_get_value("CPU", "REG_PC") ;
@@ -364,8 +364,8 @@ bne rs1 rs2 offset {
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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var offset = simcore_native_get_field_from_ir(fields, 2) ;
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- reg1 = simcore_native_get_value("BR", reg1) ;
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- reg2 = simcore_native_get_value("BR", reg2) ;
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+ reg1 = simcore_native_get_value("CPU", "BR." + reg1) ;
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+ reg2 = simcore_native_get_value("CPU", "BR." + reg2) ;
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if (reg1 != reg2)
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{
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var pc = simcore_native_get_value("CPU", "REG_PC") ;
@@ -397,10 +397,10 @@ mov r1 u32 {
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var pc = simcore_native_get_value("CPU", "REG_PC") ;
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var value = simcore_native_get_value("MEMORY", pc) ;
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- simcore_native_set_value("BR", reg1, value) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, value) ;
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simcore_native_set_value("CPU", "REG_PC", pc+4) ;
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- // simcore_native_set_value("BR ", 15, pc+4) ;
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+ // simcore_native_set_value("CPU ", "BR.15", pc+4) ;
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simcore_native_go_maddr(0) ;
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}
@@ -416,8 +416,8 @@ str reg1 (reg2) {
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var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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- var addr = simcore_native_get_value("BR", reg2) ;
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- var value1 = simcore_native_get_value("BR", reg1) ;
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+ var addr = simcore_native_get_value("CPU", "BR." + reg2) ;
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+ var value1 = simcore_native_get_value("CPU", "BR." + reg1) ;
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simcore_native_set_value("MEMORY", addr, value1) ;
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simcore_native_go_maddr(0) ;
@@ -435,9 +435,9 @@ ldr reg1 (reg2) {
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var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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- var addr = simcore_native_get_value("BR", reg2) ;
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+ var addr = simcore_native_get_value("CPU", "BR." + reg2) ;
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var value = simcore_native_get_value("MEMORY", addr) ;
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- simcore_native_set_value("BR", reg1, value) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, value) ;
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simcore_native_go_maddr(0) ;
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}
@@ -456,8 +456,8 @@ adds reg1 reg2 reg3 {
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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var reg3 = simcore_native_get_field_from_ir(fields, 2) ;
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- var result = simcore_native_get_value("BR ", reg2) + simcore_native_get_value("BR", reg3) ;
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- simcore_native_set_value("BR", reg1, result) ;
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+ var result = simcore_native_get_value("CPU ", "BR." + reg2) + simcore_native_get_value("CPU", "BR." + reg3) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, result) ;
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var flags = 0 ;
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if (result == 0) flags = flags | 0x10000000 ;
@@ -483,8 +483,8 @@ adds reg1 reg2 s16 {
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if (s16 & 0x00008000)
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s16 = s16 | 0xFFFF0000 ;
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- var result = simcore_native_get_value("BR", reg2) + s16 ;
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- simcore_native_set_value("BR", reg1, result) ;
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+ var result = simcore_native_get_value("CPU", "BR." + reg2) + s16 ;
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+ simcore_native_set_value("CPU", "BR." + reg1, result) ;
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var flags = 0 ;
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if (result == 0) flags = flags | 0x10000000 ;
@@ -506,8 +506,8 @@ mvns reg1 reg2 {
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var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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- var result = ~simcore_native_get_value("BR", reg1) ;
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- simcore_native_set_value("BR", reg1, result) ;
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+ var result = ~simcore_native_get_value("CPU", "BR." + reg1) ;
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+ simcore_native_set_value("CPU", "BR." + reg1, result) ;
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var flags = 0 ;
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if (result == 0) flags = flags | 0x10000000 ;
@@ -529,8 +529,8 @@ cmp reg reg {
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var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
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var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
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- reg1 = simcore_native_get_value("BR", reg1) ;
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- reg2 = simcore_native_get_value("BR", reg2) ;
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+ reg1 = simcore_native_get_value("CPU", "BR." + reg1) ;
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+ reg2 = simcore_native_get_value("CPU", "BR." + reg2) ;
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var result = reg1 - reg2 ;
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var flags = 0 ;
@@ -575,7 +575,7 @@ bl u16 {
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var u16 = simcore_native_get_field_from_ir(fields, 0) ;
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var pc = simcore_native_get_value("CPU", "REG_PC") ;
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- simcore_native_set_value("BR ", 14, pc) ;
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+ simcore_native_set_value("CPU ", "BR.14", pc) ;
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simcore_native_set_value("CPU", "REG_PC", u16) ;
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simcore_native_go_maddr(0) ;
@@ -591,7 +591,7 @@ bx reg1 {
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// fields is a default parameter with the instruction field information
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var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
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- var new_pc = simcore_native_get_value("BR", reg1) ;
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+ var new_pc = simcore_native_get_value("CPU", "BR." + reg1) ;
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simcore_native_set_value("CPU", "REG_PC", new_pc) ;
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simcore_native_go_maddr(0) ;
@@ -603,7 +603,7 @@ halt {
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nwords=1,
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native,
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{
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- simcore_native_set_value("BR ", 13, 0) ; // SP
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+ simcore_native_set_value("CPU ", "BR.13", 0) ; // SP
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simcore_native_set_value("CPU", "REG_PC", 0) ;
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simcore_native_go_maddr(0) ;
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