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acalderoacaldero
committed
2.3.6: minor updates on registers
1 parent ce10ee4 commit 6c19bf3

36 files changed

+1397
-1423
lines changed

‎repo/microcode/arm/ep_js.mc

Lines changed: 50 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -18,17 +18,17 @@ native
1818

1919
// push PC
2020
value = simcore_native_get_value("CPU", "REG_PC") ;
21-
var reg_sp = simcore_native_get_value("BR", 29) ;
21+
var reg_sp = simcore_native_get_value("CPU", "BR.29") ;
2222
reg_sp = reg_sp - 4 ;
2323
simcore_native_set_value("MEMORY", reg_sp, value) ;
24-
simcore_native_set_value("BR", 29, reg_sp) ;
24+
simcore_native_set_value("CPU", "BR.29", reg_sp) ;
2525

2626
// push SR
2727
value = simcore_native_get_value("CPU", "REG_SR") ;
28-
reg_sp = simcore_native_get_value("BR", 29) ;
28+
reg_sp = simcore_native_get_value("CPU", "BR.29") ;
2929
reg_sp = reg_sp - 4 ;
3030
simcore_native_set_value("MEMORY", reg_sp, value) ;
31-
simcore_native_set_value("BR", 29, reg_sp) ;
31+
simcore_native_set_value("CPU", "BR.29", reg_sp) ;
3232

3333
// MAR <- RT1*4
3434
var addr = simcore_native_get_value("CPU", "REG_RT1") ;
@@ -64,18 +64,18 @@ sret {
6464
native,
6565
{
6666
// pop SR
67-
var reg_sp = simcore_native_get_value("BR", 29) ;
67+
var reg_sp = simcore_native_get_value("CPU", "BR.29") ;
6868
var value = simcore_native_get_value("MEMORY", reg_sp) ;
6969
reg_sp = reg_sp + 4 ;
7070
simcore_native_set_value("CPU", "REG_SR", value) ;
71-
simcore_native_set_value("BR", 29, reg_sp) ;
71+
simcore_native_set_value("CPU", "BR.29", reg_sp) ;
7272

7373
// pop PC
74-
var reg_sp = simcore_native_get_value("BR", 29) ;
74+
var reg_sp = simcore_native_get_value("CPU", "BR.29") ;
7575
var value = simcore_native_get_value("MEMORY", reg_sp) ;
7676
reg_sp = reg_sp + 4 ;
7777
simcore_native_set_value("CPU", "REG_PC", value) ;
78-
simcore_native_set_value("BR", 29, reg_sp) ;
78+
simcore_native_set_value("CPU", "BR.29", reg_sp) ;
7979

8080
simcore_native_go_maddr(0) ;
8181
}
@@ -90,17 +90,17 @@ ecall {
9090

9191
// push PC
9292
var value = simcore_native_get_value("CPU", "REG_PC") ;
93-
var reg_sp = simcore_native_get_value("BR", 29) ;
93+
var reg_sp = simcore_native_get_value("CPU", "BR.29") ;
9494
reg_sp = reg_sp - 4 ;
9595
simcore_native_set_value("MEMORY", reg_sp, value) ;
96-
simcore_native_set_value("BR", 29, reg_sp) ;
96+
simcore_native_set_value("CPU", "BR.29", reg_sp) ;
9797

9898
// push SR
9999
value = simcore_native_get_value("CPU", "REG_SR") ;
100-
reg_sp = simcore_native_get_value("BR", 29) ;
100+
reg_sp = simcore_native_get_value("CPU", "BR.29") ;
101101
reg_sp = reg_sp - 4 ;
102102
simcore_native_set_value("MEMORY", reg_sp, value) ;
103-
simcore_native_set_value("BR", 29, reg_sp) ;
103+
simcore_native_set_value("CPU", "BR.29", reg_sp) ;
104104

105105
// MAR <- RT1*4
106106
var addr = simcore_native_get_value("CPU", "REG_RT1") ;
@@ -134,7 +134,7 @@ in reg val {
134134
var addr = simcore_native_get_field_from_ir(fields, 1) ;
135135

136136
var value = simcore_native_get_value("DEVICE", addr) ;
137-
simcore_native_set_value("BR", reg1, value) ;
137+
simcore_native_set_value("CPU", "BR." + reg1, value) ;
138138

139139
simcore_native_go_maddr(0) ;
140140
}
@@ -152,7 +152,7 @@ out reg val {
152152
var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
153153
var addr = simcore_native_get_field_from_ir(fields, 1) ;
154154

155-
var value = simcore_native_get_value("BR", reg1) ;
155+
var value = simcore_native_get_value("CPU", "BR." + reg1) ;
156156
simcore_native_set_value("DEVICE", addr, value) ;
157157

158158
simcore_native_go_maddr(0) ;
@@ -176,15 +176,15 @@ lb rd (rs1) {
176176
var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
177177
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
178178

179-
var b_addr = simcore_native_get_value("BR", reg2) ;
179+
var b_addr = simcore_native_get_value("CPU", "BR." + reg2) ;
180180
var w_addr = b_addr & 0xFFFFFFFC ;
181181
var w_value = simcore_native_get_value("MEMORY", w_addr) ;
182182
var b_value = b_addr & 0x00000003 ;
183183
b_value = w_value >>> (8 * b_value) ;
184184
if (b_value & 0x00000080)
185185
b_value = b_value | 0xFFFFFF00 ;
186186
else b_value = b_value & 0x000000FF ;
187-
simcore_native_set_value("BR", reg1, b_value) ;
187+
simcore_native_set_value("CPU", "BR." + reg1, b_value) ;
188188

189189
simcore_native_go_maddr(0) ;
190190
}
@@ -202,8 +202,8 @@ sb rs2 (rs1) {
202202
var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
203203
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
204204

205-
var b_addr = simcore_native_get_value("BR", reg2) ;
206-
var b_value = simcore_native_get_value("BR", reg1) ;
205+
var b_addr = simcore_native_get_value("CPU", "BR." + reg2) ;
206+
var b_value = simcore_native_get_value("CPU", "BR." + reg1) ;
207207
b_value = b_value & 0x000000FF ;
208208
var w_addr = b_addr & 0xFFFFFFFC ;
209209
var w_value = simcore_native_get_value("MEMORY", w_addr) ;
@@ -236,8 +236,8 @@ mul reg1 reg2 reg3 {
236236
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
237237
var reg3 = simcore_native_get_field_from_ir(fields, 2) ;
238238

239-
var result = simcore_native_get_value("BR", reg2) * simcore_native_get_value("BR", reg3) ;
240-
simcore_native_set_value("BR", reg1, result) ;
239+
var result = simcore_native_get_value("CPU", "BR." + reg2) * simcore_native_get_value("CPU", "BR." + reg3) ;
240+
simcore_native_set_value("CPU", "BR." + reg1, result) ;
241241

242242
simcore_native_go_maddr(0) ;
243243
}
@@ -257,8 +257,8 @@ rem reg1 reg2 reg3 {
257257
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
258258
var reg3 = simcore_native_get_field_from_ir(fields, 2) ;
259259

260-
var result = simcore_native_get_value("BR", reg2) % simcore_native_get_value("BR", reg3) ;
261-
simcore_native_set_value("BR", reg1, result) ;
260+
var result = simcore_native_get_value("CPU", "BR." + reg2) % simcore_native_get_value("CPU", "BR." + reg3) ;
261+
simcore_native_set_value("CPU", "BR." + reg1, result) ;
262262

263263
simcore_native_go_maddr(0) ;
264264
}
@@ -278,10 +278,10 @@ div reg1 reg2 reg3 {
278278
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
279279
var reg3 = simcore_native_get_field_from_ir(fields, 2) ;
280280

281-
if (simcore_native_get_value("BR", reg3) != 0)
281+
if (simcore_native_get_value("CPU", "BR." + reg3) != 0)
282282
{
283-
var result = simcore_native_get_value("BR", reg2) / simcore_native_get_value("BR", reg3) ;
284-
simcore_native_set_value("BR", reg1, result) ;
283+
var result = simcore_native_get_value("CPU", "BR." + reg2) / simcore_native_get_value("CPU", "BR." + reg3) ;
284+
simcore_native_set_value("CPU", "BR." + reg1, result) ;
285285
simcore_native_go_maddr(0) ;
286286
return ;
287287
}
@@ -290,17 +290,17 @@ div reg1 reg2 reg3 {
290290

291291
// push PC
292292
var value = simcore_native_get_value("CPU", "REG_PC") ;
293-
var reg_sp = simcore_native_get_value("BR", 29) ;
293+
var reg_sp = simcore_native_get_value("CPU", "BR.29") ;
294294
reg_sp = reg_sp - 4 ;
295295
simcore_native_set_value("MEMORY", reg_sp, value) ;
296-
simcore_native_set_value("BR", 29, reg_sp) ;
296+
simcore_native_set_value("CPU", "BR.29", reg_sp) ;
297297

298298
// push SR
299299
value = simcore_native_get_value("CPU", "REG_SR") ;
300-
reg_sp = simcore_native_get_value("BR", 29) ;
300+
reg_sp = simcore_native_get_value("CPU", "BR.29") ;
301301
reg_sp = reg_sp - 4 ;
302302
simcore_native_set_value("MEMORY", reg_sp, value) ;
303-
simcore_native_set_value("BR", 29, reg_sp) ;
303+
simcore_native_set_value("CPU", "BR.29", reg_sp) ;
304304

305305
// MAR <- RT1*4
306306
var addr = simcore_native_get_value("CPU", "REG_RT1") ;
@@ -334,8 +334,8 @@ bge rs1 rs2 offset {
334334
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
335335
var offset = simcore_native_get_field_from_ir(fields, 2) ;
336336

337-
reg1 = simcore_native_get_value("BR", reg1) ;
338-
reg2 = simcore_native_get_value("BR", reg2) ;
337+
reg1 = simcore_native_get_value("CPU", "BR." + reg1) ;
338+
reg2 = simcore_native_get_value("CPU", "BR." + reg2) ;
339339
if (reg1 >= reg2)
340340
{
341341
var pc = simcore_native_get_value("CPU", "REG_PC") ;
@@ -364,8 +364,8 @@ bne rs1 rs2 offset {
364364
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
365365
var offset = simcore_native_get_field_from_ir(fields, 2) ;
366366

367-
reg1 = simcore_native_get_value("BR", reg1) ;
368-
reg2 = simcore_native_get_value("BR", reg2) ;
367+
reg1 = simcore_native_get_value("CPU", "BR." + reg1) ;
368+
reg2 = simcore_native_get_value("CPU", "BR." + reg2) ;
369369
if (reg1 != reg2)
370370
{
371371
var pc = simcore_native_get_value("CPU", "REG_PC") ;
@@ -397,10 +397,10 @@ mov r1 u32 {
397397

398398
var pc = simcore_native_get_value("CPU", "REG_PC") ;
399399
var value = simcore_native_get_value("MEMORY", pc) ;
400-
simcore_native_set_value("BR", reg1, value) ;
400+
simcore_native_set_value("CPU", "BR." + reg1, value) ;
401401

402402
simcore_native_set_value("CPU", "REG_PC", pc+4) ;
403-
//simcore_native_set_value("BR", 15, pc+4) ;
403+
//simcore_native_set_value("CPU", "BR.15", pc+4) ;
404404

405405
simcore_native_go_maddr(0) ;
406406
}
@@ -416,8 +416,8 @@ str reg1 (reg2) {
416416
var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
417417
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
418418

419-
var addr = simcore_native_get_value("BR", reg2) ;
420-
var value1 = simcore_native_get_value("BR", reg1) ;
419+
var addr = simcore_native_get_value("CPU", "BR." + reg2) ;
420+
var value1 = simcore_native_get_value("CPU", "BR." + reg1) ;
421421
simcore_native_set_value("MEMORY", addr, value1) ;
422422

423423
simcore_native_go_maddr(0) ;
@@ -435,9 +435,9 @@ ldr reg1 (reg2) {
435435
var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
436436
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
437437

438-
var addr = simcore_native_get_value("BR", reg2) ;
438+
var addr = simcore_native_get_value("CPU", "BR." + reg2) ;
439439
var value = simcore_native_get_value("MEMORY", addr) ;
440-
simcore_native_set_value("BR", reg1, value) ;
440+
simcore_native_set_value("CPU", "BR." + reg1, value) ;
441441

442442
simcore_native_go_maddr(0) ;
443443
}
@@ -456,8 +456,8 @@ adds reg1 reg2 reg3 {
456456
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
457457
var reg3 = simcore_native_get_field_from_ir(fields, 2) ;
458458

459-
var result = simcore_native_get_value("BR", reg2) + simcore_native_get_value("BR", reg3) ;
460-
simcore_native_set_value("BR", reg1, result) ;
459+
var result = simcore_native_get_value("CPU", "BR." + reg2) + simcore_native_get_value("CPU", "BR." + reg3) ;
460+
simcore_native_set_value("CPU", "BR." + reg1, result) ;
461461

462462
var flags = 0 ;
463463
if (result == 0) flags = flags | 0x10000000 ;
@@ -483,8 +483,8 @@ adds reg1 reg2 s16 {
483483

484484
if (s16 & 0x00008000)
485485
s16 = s16 | 0xFFFF0000 ;
486-
var result = simcore_native_get_value("BR", reg2) + s16 ;
487-
simcore_native_set_value("BR", reg1, result) ;
486+
var result = simcore_native_get_value("CPU", "BR." + reg2) + s16 ;
487+
simcore_native_set_value("CPU", "BR." + reg1, result) ;
488488

489489
var flags = 0 ;
490490
if (result == 0) flags = flags | 0x10000000 ;
@@ -506,8 +506,8 @@ mvns reg1 reg2 {
506506
var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
507507
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
508508

509-
var result = ~simcore_native_get_value("BR", reg1) ;
510-
simcore_native_set_value("BR", reg1, result) ;
509+
var result = ~simcore_native_get_value("CPU", "BR." + reg1) ;
510+
simcore_native_set_value("CPU", "BR." + reg1, result) ;
511511

512512
var flags = 0 ;
513513
if (result == 0) flags = flags | 0x10000000 ;
@@ -529,8 +529,8 @@ cmp reg reg {
529529
var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
530530
var reg2 = simcore_native_get_field_from_ir(fields, 1) ;
531531

532-
reg1 = simcore_native_get_value("BR", reg1) ;
533-
reg2 = simcore_native_get_value("BR", reg2) ;
532+
reg1 = simcore_native_get_value("CPU", "BR." + reg1) ;
533+
reg2 = simcore_native_get_value("CPU", "BR." + reg2) ;
534534
var result = reg1 - reg2 ;
535535

536536
var flags = 0 ;
@@ -575,7 +575,7 @@ bl u16 {
575575
var u16 = simcore_native_get_field_from_ir(fields, 0) ;
576576

577577
var pc = simcore_native_get_value("CPU", "REG_PC") ;
578-
simcore_native_set_value("BR", 14, pc) ;
578+
simcore_native_set_value("CPU", "BR.14", pc) ;
579579
simcore_native_set_value("CPU", "REG_PC", u16) ;
580580

581581
simcore_native_go_maddr(0) ;
@@ -591,7 +591,7 @@ bx reg1 {
591591
// fields is a default parameter with the instruction field information
592592
var reg1 = simcore_native_get_field_from_ir(fields, 0) ;
593593

594-
var new_pc = simcore_native_get_value("BR", reg1) ;
594+
var new_pc = simcore_native_get_value("CPU", "BR." + reg1) ;
595595
simcore_native_set_value("CPU", "REG_PC", new_pc) ;
596596

597597
simcore_native_go_maddr(0) ;
@@ -603,7 +603,7 @@ halt {
603603
nwords=1,
604604
native,
605605
{
606-
simcore_native_set_value("BR", 13, 0) ; // SP
606+
simcore_native_set_value("CPU", "BR.13", 0) ; // SP
607607
simcore_native_set_value("CPU", "REG_PC", 0) ;
608608

609609
simcore_native_go_maddr(0) ;

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