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GHORTESSTM
authored and
GitHub Enterprise
committed
Update to v2.0.0
- upgraded to - Cube Firmware N6 V 1.1 - STEdge AI V 2.1 - STM32CUBEIDE V 1.18.1
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‎Binaries/aed_bm.bin

2.16 KB
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‎Binaries/aed_bm_lp.bin

2.13 KB
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‎Binaries/aed_tx.bin

1.81 KB
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‎Binaries/aed_tx_lp.bin

1.81 KB
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‎Binaries/flash-bin.sh

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
#!\bin\bash
22

3-
pathCubeIde="C:/ST/STM32CubeIDE_1.17.0.24B1/STM32CubeIDE"
4-
pathProg="/plugins/com.st.stm32cube.ide.mcu.externaltools.cubeprogrammer.win32_2.2.0.202409170845/tools/bin"
3+
pathCubeIde="<Path_to_cube ide>"
4+
pathProg="<Path_to_cube_programmer_plug_in>/tools/bin"
55
el=$pathCubeIde$pathProg"/ExternalLoader/MX66UW1G45G_STM32N6570-DK.stldr"
66
prog=$pathCubeIde$pathProg"/STM32_Programmer_CLI.exe"
77

‎Binaries/se_bm.bin

54.5 KB
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‎Binaries/se_bm_lp.bin

54.4 KB
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‎Binaries/se_tx.bin

54.1 KB
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‎Binaries/se_tx_lp.bin

54.1 KB
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‎Drivers/BSP/STM32N6570-DK/Release_Notes.html

Lines changed: 34 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -36,22 +36,51 @@ <h1 id="purpose">Purpose</h1>
3636
<div class="col-sm-12 col-lg-8">
3737
<h1 id="update-history">Update History</h1>
3838
<div class="collapse">
39-
<input type="checkbox" id="collapse-section1" checked aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 30-October-2024</strong></label>
39+
<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" checked aria-hidden="true"><strong>V1.1.0 / 05-February-2025</strong></label>
40+
<div>
41+
<h2 id="main-changes">Main Changes</h2>
42+
<h3 id="first-maintenance-release-of-board-drivers-supporting-stm32n6570-dk-board-mb1939c">First maintenance release of board drivers supporting <strong>STM32N6570-DK board</strong> (MB1939C)</h3>
43+
<h2 id="contents">Contents</h2>
44+
<ul>
45+
<li>Set NOR FLASH XSPI IO speed from GPIO_SPEED_FREQ_HIGH to GPIO_SPEED_FREQ_VERY_HIGH</li>
46+
<li>Optimize PSRAM access parameters in MX_XSPI_RAM_Init()</li>
47+
<li>Increase SD_WRITE_TIMEOUT and SD_READ_TIMEOUT</li>
48+
<li>Correct time-out management in BSP_SD_WriteBlocks()</li>
49+
<li>Correct BSP_SD_Init() to fix initialization issue in forcing then releasing SDMMC instances reset</li>
50+
<li>Align HAL_DCMIPP_PIPE_VsyncEventCallback() with latest ISP library tag</li>
51+
<li>Add BSP camera APIs BSP_CAMERA_FullPlanarStart(), BSP_CAMERA_SemiPlanarStart(), BSP_CAMERA_FullPlanarDoubleBufferStart() and BSP_CAMERA_SemiPlanarDoubleBufferStart()</li>
52+
</ul>
53+
<h2 id="known-limitations">Known Limitations</h2>
54+
<ul>
55+
<li>None</li>
56+
</ul>
57+
<h2 id="dependencies">Dependencies</h2>
58+
<ul>
59+
<li>ISP library v1.0.2</li>
60+
</ul>
61+
<h2 id="notes">Notes</h2>
62+
<p><em>stm32n6570_discovery_conf_template.h</em> file must be copied in user application as <em>stm32n6570_discovery_conf.h</em> with optional configuration update</p>
63+
<p><br />
64+
</p>
65+
</div>
66+
</div>
67+
<div class="collapse">
68+
<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" checked aria-hidden="true"><strong>V1.0.0 / 30-October-2024</strong></label>
4069
<div>
4170
<h2 id="first-release">First Release</h2>
4271
<h3 id="first-official-release-of-stm32cuben6-firmware-package-supporting-stm32n6xx-devices">First official release of <strong>STM32CubeN6</strong> firmware package supporting <strong>STM32N6xx</strong> devices</h3>
43-
<h2 id="contents">Contents</h2>
72+
<h2 id="contents-1">Contents</h2>
4473
<ul>
4574
<li>First official release of board drivers for <strong>STM32N6570-DK board</strong> (MB1939C)
4675
<ul>
4776
<li>in line with STM32Cube BSP drivers development guidelines (UM2298 - revision 2)</li>
4877
</ul></li>
4978
</ul>
50-
<h2 id="known-limitations">Known Limitations</h2>
79+
<h2 id="known-limitations-1">Known Limitations</h2>
5180
<p>None</p>
52-
<h2 id="dependencies">Dependencies</h2>
81+
<h2 id="dependencies-1">Dependencies</h2>
5382
<p>None</p>
54-
<h2 id="notes">Notes</h2>
83+
<h2 id="notes-1">Notes</h2>
5584
<p><em>stm32n6570_discovery_conf_template.h</em> file must be copied in user application as <em>stm32n6570_discovery_conf.h</em> with optional configuration update</p>
5685
</div>
5786
</div>

‎Drivers/BSP/STM32N6570-DK/stm32n6570_discovery.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,7 @@ typedef struct
154154
* @brief STM32N6570 Discovery BSP Driver version number
155155
*/
156156
#define STM32N6570_DK_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */
157-
#define STM32N6570_DK_BSP_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
157+
#define STM32N6570_DK_BSP_VERSION_SUB1 (0x01U) /*!< [23:16] sub1 version */
158158
#define STM32N6570_DK_BSP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
159159
#define STM32N6570_DK_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */
160160
#define STM32N6570_DK_BSP_VERSION ((STM32N6570_DK_BSP_VERSION_MAIN << 24)\

‎Drivers/BSP/STM32N6570-DK/stm32n6570_discovery_xspi.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1250,7 +1250,7 @@ __weak HAL_StatusTypeDef MX_XSPI_RAM_Init(XSPI_HandleTypeDef *hxspi, MX_XSPI_Ini
12501250
hxspi->Init.MemoryMode = HAL_XSPI_SINGLE_MEM;
12511251
hxspi->Init.MemorySize = Init->MemorySize;
12521252
hxspi->Init.MemorySelect = HAL_XSPI_CSSEL_NCS1;
1253-
hxspi->Init.ChipSelectHighTimeCycle = 1;
1253+
hxspi->Init.ChipSelectHighTimeCycle = 5;
12541254
hxspi->Init.ClockMode = HAL_XSPI_CLOCK_MODE_0;
12551255
hxspi->Init.ClockPrescaler = Init->ClockPrescaler;
12561256
hxspi->Init.SampleShifting = Init->SampleShifting;
@@ -1548,7 +1548,7 @@ static void XSPI_NOR_MspInit(const XSPI_HandleTypeDef *hxspi)
15481548
GPIO_InitStruct.Pin = XSPI_NOR_CS_PIN;
15491549
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
15501550
GPIO_InitStruct.Pull = GPIO_PULLUP;
1551-
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
1551+
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
15521552
GPIO_InitStruct.Alternate = XSPI_NOR_CS_PIN_AF;
15531553
HAL_GPIO_Init(XSPI_NOR_CS_GPIO_PORT, &GPIO_InitStruct);
15541554

‎Drivers/CMSIS/Core/Include/cachel1_armv7.h

Lines changed: 39 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
/******************************************************************************
22
* @file cachel1_armv7.h
33
* @brief CMSIS Level 1 Cache API for Armv7-M and later
4-
* @version V1.0.1
5-
* @date 19. April 2021
4+
* @version V1.0.3
5+
* @date 17. March 2023
66
******************************************************************************/
77
/*
88
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
@@ -181,30 +181,60 @@ __STATIC_FORCEINLINE void SCB_EnableDCache (void)
181181
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
182182
{
183183
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
184+
struct {
184185
uint32_t ccsidr;
185186
uint32_t sets;
186187
uint32_t ways;
188+
} locals
189+
#if ((defined(__GNUC__) || defined(__clang__)) && !defined(__OPTIMIZE__))
190+
__ALIGNED(__SCB_DCACHE_LINE_SIZE)
191+
#endif
192+
;
187193

188194
SCB->CSSELR = 0U; /* select Level 1 data cache */
189195
__DSB();
190196

191197
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
192198
__DSB();
193199

194-
ccsidr = SCB->CCSIDR;
200+
#if !defined(__OPTIMIZE__)
201+
/*
202+
* For the endless loop issue with no optimization builds.
203+
* More details, see https://github.com/ARM-software/CMSIS_5/issues/620
204+
*
205+
* The issue only happens when local variables are in stack. If
206+
* local variables are saved in general purpose register, then the function
207+
* is OK.
208+
*
209+
* When local variables are in stack, after disabling the cache, flush the
210+
* local variables cache line for data consistency.
211+
*/
212+
/* Clean and invalidate the local variable cache. */
213+
#if defined(__ICCARM__)
214+
/* As we can't align the stack to the cache line size, invalidate each of the variables */
215+
SCB->DCCIMVAC = (uint32_t)&locals.sets;
216+
SCB->DCCIMVAC = (uint32_t)&locals.ways;
217+
SCB->DCCIMVAC = (uint32_t)&locals.ccsidr;
218+
#else
219+
SCB->DCCIMVAC = (uint32_t)&locals;
220+
#endif
221+
__DSB();
222+
__ISB();
223+
#endif
195224

225+
locals.ccsidr = SCB->CCSIDR;
196226
/* clean & invalidate D-Cache */
197-
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
227+
locals.sets = (uint32_t)(CCSIDR_SETS(locals.ccsidr));
198228
do {
199-
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
229+
locals.ways = (uint32_t)(CCSIDR_WAYS(locals.ccsidr));
200230
do {
201-
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
202-
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
231+
SCB->DCCISW = (((locals.sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
232+
((locals.ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
203233
#if defined ( __CC_ARM )
204234
__schedule_barrier();
205235
#endif
206-
} while (ways-- != 0U);
207-
} while(sets-- != 0U);
236+
} while (locals.ways-- != 0U);
237+
} while(locals.sets-- != 0U);
208238

209239
__DSB();
210240
__ISB();

‎Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f16.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -285,4 +285,4 @@ void arm_cmplx_dot_prod_f16(
285285
@} end of cmplx_dot_prod group
286286
*/
287287

288-
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */
288+
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */

‎Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f16.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -238,4 +238,4 @@ void arm_cmplx_mag_f16(
238238
@} end of cmplx_mag group
239239
*/
240240

241-
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */
241+
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */

‎Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f16.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -171,4 +171,4 @@ void arm_cmplx_mag_squared_f16(
171171
@} end of cmplx_mag_squared group
172172
*/
173173

174-
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */
174+
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */

‎Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f16.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -268,4 +268,4 @@ void arm_cmplx_mult_cmplx_f16(
268268
@} end of CmplxByCmplxMult group
269269
*/
270270

271-
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */
271+
#endif /* #if defined(ARM_FLOAT16_SUPPORTED) */

‎Drivers/CMSIS/Device/ST/STM32N6xx/Include/stm32n645xx.h

Lines changed: 8 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1271,21 +1271,6 @@ typedef struct
12711271
__IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
12721272
} FDCAN_ClockCalibrationUnit_TypeDef;
12731273

1274-
/**
1275-
* @brief FD Controller Area Network Configuration
1276-
*/
1277-
typedef struct
1278-
{
1279-
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
1280-
uint32_t RESERVED1[128]; /*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
1281-
__IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */
1282-
uint32_t RESERVED2[58]; /*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
1283-
__IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */
1284-
__IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */
1285-
__IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */
1286-
__IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */
1287-
} FDCAN_Config_TypeDef;
1288-
12891274
/**
12901275
* @brief Flexible Memory Controller Bank1
12911276
*/
@@ -2586,14 +2571,14 @@ typedef struct
25862571
__IO uint32_t ICNEWRCR; /*!< SYSCFG AHB-AXI bridge early write response, Address offset: 0x34 */
25872572
__IO uint32_t ICNCGCR; /*!< SYSCFG ICN clock gating control register, Address offset: 0x38 */
25882573
uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x3C-0x40 */
2589-
__IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x44 */
2590-
__IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x48 */
2591-
__IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x4C */
2592-
__IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x50 */
2593-
__IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x54 */
2594-
__IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x58 */
2595-
__IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x5C */
2596-
__IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x60 */
2574+
__IO uint32_t VDDIO4CCCR; /*!< SYSCFG VDDIO4 compensation cell control register, Address offset: 0x44 */
2575+
__IO uint32_t VDDIO4CCSR; /*!< SYSCFG VDDIO4 compensation cell status register, Address offset: 0x48 */
2576+
__IO uint32_t VDDIO5CCCR; /*!< SYSCFG VDDIO5 compensation cell control register, Address offset: 0x4C */
2577+
__IO uint32_t VDDIO5CCSR; /*!< SYSCFG VDDIO5 compensation cell status register, Address offset: 0x50 */
2578+
__IO uint32_t VDDIO2CCCR; /*!< SYSCFG VDDIO2 compensation cell control register, Address offset: 0x54 */
2579+
__IO uint32_t VDDIO2CCSR; /*!< SYSCFG VDDIO2 compensation cell status register, Address offset: 0x58 */
2580+
__IO uint32_t VDDIO3CCCR; /*!< SYSCFG VDDIO3 compensation cell control register, Address offset: 0x5C */
2581+
__IO uint32_t VDDIO3CCSR; /*!< SYSCFG VDDIO3 compensation cell status register, Address offset: 0x60 */
25972582
__IO uint32_t VDDCCCR; /*!< SYSCFG VDD compensation cell control register, Address offset: 0x64 */
25982583
__IO uint32_t VDDCCSR; /*!< SYSCFG VDD compensation cell status register, Address offset: 0x68 */
25992584
__IO uint32_t CBR; /*!< SYSCFG control timer break register, Address offset: 0x6C */
@@ -2932,7 +2917,6 @@ typedef struct
29322917
#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL)
29332918
#define MDIOS_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL)
29342919
#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA000UL)
2935-
#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA100UL)
29362920
#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL)
29372921
#define FDCAN_CCU_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL)
29382922
#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xC000UL)
@@ -3205,7 +3189,6 @@ typedef struct
32053189
#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL)
32063190
#define MDIOS_BASE_S (APB1PERIPH_BASE_S + 0x9400UL)
32073191
#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA000UL)
3208-
#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA100UL)
32093192
#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA400UL)
32103193
#define FDCAN_CCU_BASE_S (APB1PERIPH_BASE_S + 0xA800UL)
32113194
#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xC000UL)
@@ -3441,7 +3424,6 @@ typedef struct
34413424
#define FDCAN2_NS ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_NS)
34423425
#define FDCAN3_NS ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_NS)
34433426
#define FDCAN_CCU_NS ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_NS)
3444-
#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS)
34453427
#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS)
34463428
#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS)
34473429
#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS)
@@ -3638,7 +3620,6 @@ typedef struct
36383620
#define FDCAN2_S ((FDCAN_GlobalTypeDef *) FDCAN2_BASE_S)
36393621
#define FDCAN3_S ((FDCAN_GlobalTypeDef *) FDCAN3_BASE_S)
36403622
#define FDCAN_CCU_S ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE_S)
3641-
#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S)
36423623
#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S)
36433624
#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S)
36443625
#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S)
@@ -3885,9 +3866,6 @@ typedef struct
38853866
#define FDCAN_CCU FDCAN_CCU_S
38863867
#define FDCAN_CCU_BASE FDCAN_CCU_BASE_S
38873868

3888-
#define FDCAN_CONFIG FDCAN_CONFIG_S
3889-
#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S
3890-
38913869
#define FMC_R_BASE FMC_R_BASE_S
38923870

38933871
#define FMC_Bank1E_R FMC_Bank1E_R_S
@@ -4492,9 +4470,6 @@ typedef struct
44924470
#define FDCAN_CCU FDCAN_CCU_NS
44934471
#define FDCAN_CCU_BASE FDCAN_CCU_BASE_NS
44944472

4495-
#define FDCAN_CONFIG FDCAN_CONFIG_NS
4496-
#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS
4497-
44984473
#define FMC_R_BASE FMC_R_BASE_NS
44994474
#define FMC_R_BASE_BASE FMC_R_BASE_BASE_NS
45004475

@@ -39778,8 +39753,6 @@ typedef struct
3977839753
((INSTANCE) == FDCAN2_S) || ((INSTANCE) == FDCAN2_NS) || \
3977939754
((INSTANCE) == FDCAN3_S) || ((INSTANCE) == FDCAN3_NS))
3978039755

39781-
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN_CONFIG_S) || ((INSTANCE) == FDCAN_CONFIG_NS))
39782-
3978339756
#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_S)
3978439757

3978539758
/******************************* GFXMMU Instance *****************************/
@@ -40662,8 +40635,6 @@ typedef struct
4066240635
((INSTANCE) == FDCAN2_NS) || \
4066340636
((INSTANCE) == FDCAN3_NS))
4066440637

40665-
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG_NS)
40666-
4066740638
#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1_NS)
4066840639

4066940640
/******************************* GFXMMU Instance *****************************/

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